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  emergency light flash mcu HT45FH4J revision: v1.10 date: de ? e ?? e ? 1 ?? ? 01 ? de ? e ?? e ? 1 ?? ? 01 ?
rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 3 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu table of contents eates cpu featu ? es ......................................................................................................................... ? pe ? iphe ? al featu ? es ................................................................................................................. ? e ? e ? gen ? y light appli ? ation featu ? es ............. ....................................................................... ? gene?al des??iption ........................................................................................ 7 blo?k diag?a? .................................................................................................. 7 pin assign?ent ........... ..................................................................................... 8 pin des??iption s .............................................................................................. 9 a?solute maxi?u? ratings ........................................................................... 11 d.c. cha?a?te?isti?s ........................................................................................ 11 a.c. cha?a?te?isti?s ....................................................................................... 13 lvd&lvr ele?t?i?al cha?a?te?isti?s ............................................................ 1? adc ele?t?i?al cha?a?te?isti?s ... .................................................................. 15 ldo regulato? ele?t?i?al cha?a?te?isti?s ................................................... 15 ove? cu??ent p?ete?tion ele?t?i?al cha?a?te?isti?s .................................... 1? powe?-on reset ele?t?i?al cha?a?te?isti?s ........... ....................................... 1? syste? a??hite?tu?e ...................................................................................... 17 clo ? king and pipelining ......................................................................................................... 17 p ? og ? a ? counte ? ................................................................................................................... 18 sta ? k ..................................................................................................................................... 19 a ? ith ? eti ? and logi ? unit C alu ........................................................................................... 19 flash p?og?a? me?o?y ................................................................................. ?0 st ? u ? tu ? e ................................................................................................................................ ? 0 spe ? ial ve ? to ? s ..................................................................................................................... ? 0 look-up ta ? le ............. ........................................................................................................... ? 1 ta ? le p ? og ? a ? exa ? ple ........................................................................................................ ?? in ci ?? uit p ? og ? a ?? ing ......................................................................................................... ? 3 on-chip de ? ug suppo ? t C ocds ......................................................................................... ?? ram data me?o?y ......................................................................................... ?5 st ? u ? tu ? e ................................................................................................................................ ? 5 spe?ial fun?tion registe? des??iption ........................................................ ?7 indi ? e ? t add ? essing registe ? s C iar0 ? iar1 ......................................................................... ? 7 me ? o ? y pointe ? s C mp0 ? mp1 .............................................................................................. ? 7 bank pointe ? C bp ................................................................................................................. ? 8 a ?? u ? ulato ? C acc ............................................................................................................... ? 8 p ? og ? a ? counte ? low registe ? C pcl .................................................................................. ? 8 look-up ta ? le registe ? s C tblp ? tbhp ? tblh ..................................................................... ? 8 status registe ? C status .................................................................................................... ? 9
rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 3 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu eeprom data memory ........... ....................................................................... 31 eeprom data me ? o ? y st ? u ? tu ? e ........................................................................................ 31 eeprom registe ? s ............ .................................................................................................. 31 reading data f ? o ? the eeprom ........................................................................................ 33 w ? iting data to the eeprom ................................................................................................ 33 w ? ite p ? ote ? tion ..................................................................................................................... 33 eeprom inte ?? upt ............. ................................................................................................... 33 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 3 ? oscillator ........................................................................................................ 35 os ? illato ? ove ? view ............. .................................................................................................. 35 system clock confgurations ................................................................................................ 35 inte ? nal rc os ? illato ? C hirc ............. .................................................................................. 3 ? inte ? nal 3 ? khz os ? illato ? C lirc ........................................................................................... 3 ? operating modes and system clocks ......................................................... 36 syste ? clo ? ks ...................................................................................................................... 3 ? syste ? ope ? ation modes ...................................................................................................... 37 cont ? ol registe ? .................................................................................................................... 39 ope ? ating mode swit ? hing ................................................................................................... ? 1 normal mode to slow mode swit ? hing ........................................................................... ? 1 slow mode to normal mode swit ? hing .......................................................................... ?? ente ? ing the sleep mode .................................................................................................... ?? ente ? ing the idle0 mode ...................................................................................................... ? 3 ente ? ing the idle1 mode ...................................................................................................... ? 3 stand ? y cu ?? ent conside ? ations ........................................................................................... ? 3 wake-up ................................................................................................................................ ?? watchdog timer ........... .................................................................................. 45 wat ? hdog ti ? e ? clo ? k sou ?? e .............................................................................................. ? 5 wat ? hdog ti ? e ? cont ? ol registe ? ............. ............................................................................ ? 5 wat ? hdog ti ? e ? ope ? ation ................................................................................................... ?? reset and initialisation .................................................................................. 47 reset fun ? tions ............. ....................................................................................................... ? 7 reset initial conditions ......................................................................................................... 50 input/output ports ......................................................................................... 53 pull-high resisto ? s ................................................................................................................ 53 po ? t a wake-up ............. ........................................................................................................ 5 ? i/o po ? t cont ? ol registe ? s ..................................................................................................... 5 ? pin- sha ? ed fun ? tions ............. ............................................................................................... 55 pin- sha ? ed fun ? tion sele ? tion registe ? s ............. ................................................................. 55 i/o pin st ? u ? tu ? es .................................................................................................................. 5 ? p ? og ? a ?? ing conside ? ations ............. ................................................................................... 57
rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 5 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu timer modules C tm .......... ............................................................................ 58 int ? odu ? tion ........................................................................................................................... 58 tm ope ? ation ............. ........................................................................................................... 58 tm clo ? k sou ?? e ............. ...................................................................................................... 58 tm inte ?? upts ......................................................................................................................... 58 tm exte ? nal pins ................................................................................................................... 59 tm input/output pin cont ? ol ................................................................................................. 59 p ? og ? a ?? ing conside ? ations ............. ................................................................................... ? 0 periodic type tm C ptm ................................................................................ 61 pe ? iodi ? tm ope ? ation ............. ............................................................................................. ? 1 pe ? iodi ? type tm registe ? des ?? iption ................................................................................. ?? pe ? iodi ? type tm ope ? ating modes ...................................................................................... ?? co ? pa ? e mat ? h output mode ............................................................................................... ?? ti ? e ? /counte ? mode ............................................................................................................. ? 9 pwm output mode ............. ................................................................................................... ? 9 single pulse output mode .................................................................................................... 71 captu ? e input mode .............................................................................................................. 73 analog to digital converter .......... ................................................................ 75 a/d ove ? view ............. ........................................................................................................... 75 a/d conve ? te ? registe ? des ?? iption ...................................................................................... 7 ? a/d conve ? te ? data registe ? s C sado l ? sadoh ............. ................................................... 7 ? a/d conve ? te ? cont ? ol registe ? s C sa dc0 ? sadc1 ............................................................. 7 ? a/d ope ? ation ....................................................................................................................... 78 a/d input pins ............. .......................................................................................................... 80 c onve ? sion rate and ti ? ing diag ? a ? .................................................................................. 80 su ?? a ? y of a/d conve ? sion steps ............. .......................................................................... 81 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 8 ? a/d t ? ansfe ? fun ? tion ............. .............................................................................................. 8 ? a/d p ? og ? a ?? ing exa ? ples ................................................................................................. 83 complementary pwm output ....................................................................... 85 over current protection ............................................................................... 87 o ve ? c u ?? ent p ? ote ? tion ope ? ation ....................................................................................... 87 o ve ? c u ?? ent p ? ote ? tion cont ? ol registe ? s ........................................................................... 88 i nput voltage range .............................................................................................................. 91 offset cali ?? ation .................................................................................................................. 9 ? emergency light application description .................................................. 93 cha ? ge unde ? no ?? al mains supply ............. ........................................................................ 93 analog batte ? y boost cha ? ge unde ? no ?? al mains supply ................................................. 93 buzze ? d ? iving ....................................................................................................................... 93 led d ? iving ........................................................................................................................... 93 high voltage mos .......................................................................................... 94 cont ? ol registe ? s .................................................................................................................. 9 ?
rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 5 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu interrupts ........................................................................................................ 98 inte ?? upt registe ? s ................................................................................................................. 98 inte ?? upt ope ? ation .............................................................................................................. 103 exte ? nal inte ?? upt ............. .................................................................................................... 10 ? ocp inte ?? upt ...................................................................................................................... 105 multi-fun ? tion inte ?? upt ........................................................................................................ 105 a/d conve ? te ? inte ?? upt ....................................................................................................... 105 ti ? e base inte ?? upts ........................................................................................................... 10 ? eeprom inte ?? upt ............. ................................................................................................. 107 lvd inte ?? upt ....................................................................................................................... 107 tm inte ?? upt s ....................................................................................................................... 107 inte ?? upt wake-up fun ? tion ................................................................................................. 108 p ? og ? a ?? ing conside ? ations ............. ................................................................................. 108 low voltage detector C lvd .......... ............................................................. 109 lvd registe ? ............. .......................................................................................................... 109 lvd ope ? ation ...................................................................................................................... 110 confguration option ........... ......................................................................... 110 application circuit ........................................................................................ 111 e ? e ? gen ? y light appli ? ation ci ?? uit (led unde ? 0. ? w) ............. .......................................... 111 e ? e ? gen ? y light appli ? ation ci ?? uit (led ove ? 1w) ............................................................ 11 ? instruction set ............................................................................................... 113 int ? odu ? tion .......................................................................................................................... 113 inst ? u ? tion ti ? ing ................................................................................................................. 113 moving and t ? ansfe ?? ing data .............................................................................................. 113 a ? ith ? eti ? ope ? ations ........................................................................................................... 113 logi ? al and rotate ope ? ation .............................................................................................. 11 ? b ? an ? hes and cont ? ol t ? ansfe ? ............................................................................................ 11 ? bit ope ? ations ...................................................................................................................... 11 ? ta ? le read ope ? ations ........................................................................................................ 11 ? othe ? ope ? ations ............. ..................................................................................................... 11 ? instruction set summary .......... ................................................................... 115 ta ? le conventions ................................................................................................................ 115 instruction defnition .................................................................................... 117 package information ................................................................................... 126 1 ? -pin nsop (150 ? il) outline di ? ensions ......................................................................... 1 ? 7 ? 0 -pin ssop (150 ? il) outline di ? ensions ......................................................................... 1 ? 8
rev. 1.10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 7 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu features cpu features ? high v oltage input (up to 12v) to the integrated ldo and outputs 5v to supply mcu operating voltage ? up to 0. 2 s instruction cycle with 20 mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillators internal 12/16/20mhz hight speed rc -- hirc internal low speed 32khz rc -- lirc ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 4 -level subroutine nesting ? bit manipulation instr uction peripheral features ? flash p rogra m memory: 2 k16 ? ram data memory: 1 288 ? true eeprom memory: 648 ? watchdog t imer function ? 12 bidirectional i/o lines ? two pin-shared external interrupts ? multiple t imer module for time measure, input capture, compare match output, pwm output function or single pulse output function ? t wo c omplementary pwm output with dead time control ? o ver current protection (ocp) with interrupt ? dual t ime-base functions for generation of fxed time interrupt signals ? 6 external channel s 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? package: 16-pin n so p, 20-pin ssop emergency light application features ? one integ rate d ldo: 5v output to supply operating voltage for the mcu, led indicator and other circuits. ? one integrated resistor divider, its dc/dc boost voltage is used for close loop control ? one internal pmos and driving an external nmos can implement the dc/dc boost and buck control ? internal led driving circuit (0.6w) ? supports an additional external nmos for high power led driving (over 0.6w) ? high voltage and high current output for buzzer driving (140ma) ? one internal switch for emergency light product battery and led lighting self-test function
rev. 1.10 ? de?e??e? 1?? ?01? rev. 1.10 7 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu general description this device is an emer gency light assp flash mcu. the device includes 2k16 of flash program memory, 128 bytes of data memory and 64 bytes of data eeprom. the internal ldo provides a maximum input voltage of 12v and outputs a 5v voltage with a current of 50ma which can then be provided to the mcu and peripheral circuits. additional features include one fully integrated high accuracy rc oscillator with three fxed frequencies of either 12mhz, 16mhz or 20mhz, an internal 6-channel 12-bit a/d converter and three 10-bit periodic t imers. one of these t imers can be used to generate two complementary pwm outputs which are used for the required dc/dc boost and buck circuitry. a range of protection features are provided, such as over current protection, low v oltage detector a nd l ow v oltage re set, whi ch a re use d for syst em vol tage m onitoring. if t he syst em voltage falls below the l vr value, the device will be automatically reset to reduce the possibility of unstable operations. in the traditional emer gency light applications , a microcontroller us ually requires additional transistors to drive leds, buzzers as well as the boost and buck circuits. however , this new device includes a powerful driving capability , it can directly drive leds with a current of 100ma and buzzers wi th a c urrent of 140m a. duri ng ba ttery c harging a nd di scharging, t he c omplementary pwm outputs with a dead time insertion, are used to drive an internal pmos transistor and an external nmos transistor to implem ent the synchronous rectifcation function. the device is able to reduce the power consumption to a minimum, improve the operating effciency and extend the led illumination t ime. as for prot ection fe atures, t he ove r c urrent prot ection c ircuitry e nsures t hat t he leds and the battery remain free from damage when over current occurs. block diagram 8-bit risc mcu core flash program memory eeprom data memory flash/eeprom programming circuitry ram data memory time base low voltage detect watchdog timer interrupt controller reset circuit internal rc oscillators 12-bit a/d converter i/o over current protection low voltage reset vdd 5v ldo (50ma) boot/buck control buzzer driver (140ma) led driver (100ma) level shift level shift timer module timer module timer module level shift led_out bz bat_in ocp0/1 anx intx hv_in (7~12v input)
rev. 1.10 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 9 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu pin assignment 1? 15 1? 13 1? 11 10 9 1 ? 3 ? 5 ? 7 8 bat _ in bz led _ out hvss pa 0/ icpda / ocdsda pa ?/ icpck / ocdsck pa 1/ an 0/ tp 0 pa 3/ an 1/ vref / int 0/ tck 0 pa ?/ an ?/ tp 1 pa 5/ an 3/ ocp 1/ int 1/ tck 1 pa ?/ an ?/ ocp 0/ tp ? vss pa 7/ an 5/ pwm 0l / tck ? vdd / ldo _ out hv _ in / ldo _ in hv _ out ht 45fh 4j/ ht 45vh 4j 16 nsop -a bat _ in bz led _ out hvss pa 0/ icpda / ocdsda pa ?/ icpck / ocdsck pb 0/ pwm 0h pb 1 pa ?/ an ?/ tp 1 pa 5/ an 3/ ocp 1/ int 1/ tck 1 pa ?/ an ?/ ocp 0/ tp ? vss pa 7/ an 5/ pwm 0l/ tck ? vdd / ldo _ out hv _ in / ldo _ in hv _ out ht 45fh 4j/ ht 45vh 4j 20 ssop -a pb ? pb 3 pa 1/ an 0/ tp 0 pa 3/ an 1/ vref / int 0/ tck 0 ?0 19 18 17 1? 15 1? 13 1? 11 1 ? 3 ? 5 ? 7 8 9 10 note: 1 . if the pin-shared pin functions have multiple outputs simultaneously , the desired pin-shared function is determined by the corresponding software control bits . 2 . t he a ctual de vice a nd i ts e quivalent ocds ev device share same package t ype, however the ocds ev device part number is ht45v. pins ocdsck and ocdsda which are pin-shared with pa2 and pa0 are only used for the ocds ev device .
rev. 1.10 8 de?e??e? 1?? ?01? rev. 1.10 9 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu pin description s with the exception of the power pins and some relevant transformer control pins, all pins on th is device can be referenced by their port name, e.g. p a0, p a1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, t imer module pins etc. t he function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. as the pin description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. pin name function opt i/t o/t description pa0 /icpda/ ocdsda pa0 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. icpda st cmos in- ? i ?? uit p ? og ? a ?? ing data/add ? ess pin ocdsda st cmos on- ? hip de ? ug suppo ? t data/add ? ess pin ? only fo ? ev ic pa1/an 0/tp0 pa1 papu pawu ctrl3 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an0 ctrl3 an a/d c onve ? te ? input 0 tp0 ctrl3 st cmos tm0 i/o pa ? / icpck/ ocdsck pa ? papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. icpck st in- ? i ?? uit p ? og ? a ?? ing ? lo ? k pin ocdsck st on- ? hip de ? ug suppo ? t ? lo ? k pin ? only fo ? ev ic pa3/ an1/vref/ int0/tck0 pa3 papu pawu ctrl3 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an1 ctrl3 an a/d c onve ? te ? input 1 vref ctrl3 an a/d c onve ? te ? ? efe ? en ? e voltage input int0 ctrl3 integ intc1 st exte ? nal inte ?? upt 0 tck0 ctrl3 tm0c0 st tm0 ? lo ? k input pa ? /an ? /tp1 pa ? papu pawu ctrl3 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an ? ctrl3 an a/d c onve ? te ? input ? tp1 ctrl3 st cmos tm1 i/o pa5/ an3/ocp1/ int1/tck1 pa 5 papu pawu ctrl3 st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an3 ctrl3 an a/d c onve ? te ? input 3 ocp1 ctrl3 an ove ? ? u ?? ent p ? ote ? tion input int1 ctrl3 integ intc1 st exte ? nal inte ?? upt 1 tck1 ctrl3 tm1c0 st tm1 ? lo ? k input
rev. 1.10 10 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 11 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu pin name function opt i/t o/t description pa ? / an ? /ocp0/ tp ? pa ? papu pawu ctrl ? st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an ? ctrl ? an a/d c onve ? te ? input ? ocp0 ctrl ? an ove ? ? u ?? ent p ? ote ? tion input tp ? ctrl ? st cmos tm ? i/o pa7/ an5/ pwm0l/ tck ? pa 7 papu pawu ctrl ? st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up and wake-up. an5 ctrl ? an a/d c onve ? te ? input 5 pwm0l ctrl ? cmos co ? ple ? enta ? y pwm0 output tck ? ctrl ? tm ? c0 st tm ? ? lo ? k input pb0/pwm0h pb0 pbpu ctrl ? st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up pwm0h ctrl ? cmos co ? ple ? enta ? y pwm0 output pb1~pb3 pb1~pb3 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-up vdd/ldo_out vdd pwr p ositive powe ? supply ldo_out pwr 5v ldo output hv_in/ldo_in ldo_in pwr ldo input vss vss pwr nega tive powe ? supply high voltage i/o ports bz bz cmos buzze ? d ? ive ? output bat_in bat_in pmos pmos batte ? y input led_out led_out pmos led d ? ive ? output high voltage power hv_in/ldo_in hv_in pwr p ositive powe ? supply (fo ? high voltage) hv_out hv_out pwr high voltage output hvss hvss pwr nega tive powe ? supply (fo ? high voltage) note : i/t: input type o/t: output type opt : optional by register option pwr: power st: schmitt t rigger input cmos: cmos output pmos: pmos output an: analog signal
rev. 1.10 10 de?e??e? 1?? ?01? rev. 1.10 11 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i ol t otal .............. ................................................................................................... .................... 80ma i oh t otal .............. ...................................................................................................................... -80ma total power dissipation .............. ........................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics ta = ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v cc analog ope ? ation voltage hv_in pin input voltage 5 7 1 ? v v dd ope ? ation voltage f sys =1 ? /1 ? / ? 0mhz -3% 5 +3% v i dd1 ope ? ation cu ?? ent ? no ?? al mode f sys =f h 5v no load ? f h =1 ? mhz ? adc off ? wdt ena ? le ? .5 3.8 ? a no load ? f h =1 ? mhz ? adc off ? wdt ena ? le 3.3 5.0 ? a no load ? f h = ? 0mhz ? adc off ? wdt ena ? le ? . ? ? .3 ? a i dd ? ope ? ation cu ?? ent ? slow mode ? f sys =f l =f lirc ? f sub =f lirc 5v no load ? f sys =f lirc ? adc off ? wdt ena ? le 55 95 i dd3 ope ? ation cu ?? ent ? no ?? al mode f h = 1 ? mhz 5v no load ? f sys =f h / ? ? adc off ? wdt ena ? le ? . ? 3.3 ? a no load ? f sys =f h / ?? adc off ? wdt ena ? le 1.5 ? . ? 5 ? a no load ? f sys =f h /8 ? adc off ? wdt ena ? le 1. ? 1.8 ? a no load ? f sys =f h /1 ?? adc off ? wdt ena ? le 1.1 1. ? 5 ? a no load ? f sys =f h /3 ?? adc off ? wdt ena ? le 1.0 1.5 ? a no load ? f sys =f h / ??? adc off ? wdt ena ? le 0.9 1.35 ? a
rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 13 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu symbol parameter test conditions min. typ. max. unit v dd conditions i dd ? ope ? ation cu ?? ent ? no ?? al mode f h = ? 0 mhz 5v no load ? f sys =f h / ? ? adc off ? wdt ena ? le ? .7 ? .1 ? a no load ? f sys =f h / ?? adc off ? wdt ena ? le 1. ? ? . ? ? a no load ? f sys =f h /8 ? adc off ? wdt ena ? le 1.5 ? .3 ? a no load ? f sys =f h /1 ?? adc off ? wdt ena ? le 1.3 1.95 ? a no load ? f sys =f h /3 ?? adc off ? wdt ena ? le 1. ? 1.8 ? a no load ? f sys =f h / ??? adc off ? wdt ena ? le 1.15 1.75 ? a i idle0 idle0 mode stand ? y cu ?? ent (lirc on) 5v no load ? adc off ? wdt ena ? le ? lvr disa ? le ?? . ? 38 a i idle1 1 idle1 mode stand ? y cu ?? ent 5v no load ? adc off ? wdt ena ? le ? f sys = 1 ? mhz on 1. ? ? . ? ? a i idle1 ? idle1 mode stand ? y cu ?? ent 5v no load ? adc off ? wdt ena ? le ? f sys = 1 ? mhz on ? .0 ? .0 ? a i idle13 idle1 mode stand ? y cu ?? ent 5v no load ? adc off ? wdt ena ? le ? f sys = ? 0mhz on ? . 5 5.0 ? a i sleep sleep mode stand ? y cu ?? ent (lirc on) 5v no load ? adc off ? wdt ena ? le ? lvr disa ? le ? 8 ? 0 a v il input low voltage fo ? i/o po ? ts o ? input pins 5v 0 1.5 v 0 0. ? v dd v v ih input high voltage fo ? i/o po ? ts o ? input pins 5v 3.5 5.0 v 0.8v dd v dd v i ol1 i/o po ? t sink cu ?? ent ( ex ? ept fo ? bz ? bat_in ? led_out ? pa7 ) 5v v ol =0.1v dd 1 ? 3 ? ? a i oh1 i/o po ? t sou ?? e cu ?? ent ( ex ? ept fo ? bz ? bat_in ? led_out ? pa7 ) 5v v oh =0.9v dd ? 1 ? ? a i ol ? i/o po ? t sink cu ?? ent ( pa7 ) 5v v ol =0.1v dd ? 0 80 ? a i oh ? i/o po ? t sou ?? e cu ?? ent ( pa7 ) 5v v oh =0.9v dd ? 0 80 ? a r ph pull-high resistan ? e fo ? i/o po ? ts 5v 10 30 50 k high voltage i/o ports i ol3 i/o po ? t sink cu ?? ent (bz) ? .5v v ol =0.1hv_out 115 1 ? 0 ? a i oh3 i/o po ? t sou ?? e cu ?? ent (bz) ? .5v v oh =0.9hv_out -5% 10 ? a i oh ? i/o po ? t sou ?? e cu ?? ent (bat_in) ? .5v v oh =hv_out-0.5 ? 35 ? a i oh5 i/o po ? t sou ?? e cu ?? ent (led_out) ? .5v v oh =hv_out-0.5 100 ? a
rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 13 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu a.c. characteristics ta = ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu ope ? ating clo ? k 5v3% dc 1 ? mhz dc 1 ? mhz dc ? 0 mhz f sys syste ? clo ? k (hirc) 5v3% 1 ? mhz 1 ? mhz ? 0 mhz f hirc hirc f ? equen ? y (note) 5v3% ta= ? 5c - ? % 1 ? /1 ? / ? 0 + ? % mhz ta=- ? 0c~85c -5% 1 ? /1 ? / ? 0 +5% mhz f lirc lirc f ? equen ? y 5v3% ta= ? 5c -10% 3 ? +10% khz ta=- ? 0c ~ 85c -30% 3 ? + ? 0% khz t timer tckn input pin mini ? u ? pulse width 30 ns t int inte ?? upt mini ? u ? pulse width 1 3.3 5 s t eerd eeprom read ti ? e ? ? t sys t eewr eeprom w ? ite ti ? e ? ? ? s t sst syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt ? f sys off at halt state) f sys =hirc 1 ? t hirc f sys =lirc ? t sys syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt ? f sys on at halt state) f sys =hirc ? t hirc t rstd syste ? reset delay ti ? e (powe ? on reset ? lvr h/w reset ? lvr s/w reset ? wdt s/w reset) ? 5 50 100 ? s syste ? reset delay ti ? e (wdt no ?? al reset) 8.3 1 ? .7 33.3 ? s 1rwh w ?? i ?? w +?5& i +?5& 7 r pdlqwdlq wkh dffxudf ri wkh lqwhuqdo +?5& rvfloodwru iuhtxhqf d ) ghfrxsolqj fdsdflwru vkrxog be fhfh hhh fh fh h hfh h
rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 15 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu lvd&lvr electrical characteristics ta = ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr 1 low voltage reset voltage lvr ena ? le ? ? . 1v -5% ? . 1 +5% v v lvr ? lvr ena ? le ? ? . 55v ? .55 v v lvr 3 lvr ena ? le ? 3.15v 3.15 v v lvr ? lvr ena ? le ? 3.8v 3.8 v v lvd 1 low voltage dete ? to ? voltage lvden= 1 ? v lvd = ? . 0v -5% ? . 0 +5% v v lvd ? lvden= 1 ? v lvd = ? . ? v ? . ? v v lvd 3 lvden= 1 ? v lvd = ? . ? v ? . ? v v lvd ? lvden= 1 ? v lvd = ? .7 v ? .7 v v lvd 5 lvden= 1 ? v lvd = 3.0v 3.0 v v lvd ? lvden= 1 ? v lvd = 3.3v 3.3 v v lvd 7 lvden= 1 ? v lvd = 3. ? v 3. ? v v lvd 8 lvden= 1 ? v lvd = ? .0v ? .0 v i lv r additional powe ? consu ? ption if lv r is used 5v3% lv r disable lvr ena ? le ? 0 90 a i lvd additional powe ? consu ? ption if lvd is used 5v3% lvd disable lvd enable (lvr dis a ? le) 75 115 a lvd disable lvd enable (lvr ena ? le) ? 0 90 a t lvr low voltage width to reset 1 ? 0 ?? 0 ? 80 s t lvd low voltage width to inte ?? upt ? 0 1 ? 0 ?? 0 s t lvds lvdo sta ? le ti ? e fo ? lvr ena ? le ? lvd off on 5 s fo ? lvr dis a ? le ? lvd off on 15 s t sreset softwa ? e reset width to reset ? 5 90 1 ? 0 s ote v lvr and v lvd are the lvr and lvd oltage when the v dd oltage drops.
rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 15 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu adc electrical characteristics ta = ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions a v dd a/d conve ? te ? ope ? ation voltage ? .7 5 5.5 v v ref a/d conve ? te ? refe ? en ? e voltage ? .0 av dd v v ad a/d conve ? te ? input voltage 0 av dd /v ref v i adc additional powe ? consu ? ption if a/d conve ? te ? is used 5v no load (t adck = 0.5s) 1.5 3.0 ? a dnl diffe ? ential non-linea ? ity 5v v ref =av dd =v dd ? t adck = 0.5s -3 +5 lsb v ref =av dd =v dd ? t adck = 10s -3 +5 lsb inl integ ? al non-linea ? ity 5v v ref =av dd =v dd ? t adck = 0.5s -5 + ? lsb v ref =av dd =v dd ? t adck = 10s -5 + ? lsb t adck a/d conve ? te ? clo ? k pe ? iod 0.5 10 s t adc a/d conve ? sion ti ? e (in ? lude sa ? ple and hold ti ? e) 1 ? - ? it adc 1 ? ? 0 t adck t ads a/d conve ? te ? sa ? pling ti ? e 1 ? - ? it adc ? t adck t on ? st a/d conve ? te ? on-to-sta ? t ti ? e ? s ldo regulator electrical characteristics v in =v out + ? .0v ? i o =1 ? a ? ta= ? 5 c ? unless othe ? wise specife d symbol parameter test conditions min. typ. max. unit v dd conditions v in input voltage 7 1 ? v v out output voltage -3% 5 3% v v out output voltage tole ? an ? e 7v~1 ? v i o =5 0 ? a ? ta= ? 5 c -3.0 3.0 % i o =5 0 ? a ? ta= - ? 0 c~85c (ex ? ept ? 5 c) -5.0 5.0 % v load load regulation 7v~1 ? v 1mai o 5 0 ? a 0.18 0. 3 ? % ? a v drop d ? op out voltage 7v~1 ? v i o =1 ? a ? v o = ? % 100 ? v i ss quiens ? ent cu ?? ent 7v~1 ? v i o =0 ? a ? 5 ? 5 a v line line regulation 7v~1 ? v 1.0v+v out v in 1 ? v ? i o =1 ? a 0. ? %/v v out /ta temperature coeffcient 7v~1 ? v i o =5 0 ? a 0.5 ? ? v/ c 1rwh 7kh /'? fdq surylgh d p ordg dqg d fxuuhqw olplw ixqfwlrq 7kh /'? lv dozdv hqdeohg zlwkrxw d frqwuro vljqdo lw uhtxluhv dq h[whuqdo m m m
rev. 1.10 1 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 17 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu over current pretection electrical characteristics ta = ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions i op ope ? ation cu ?? ent 5v enocp[1:0]=01 ? dac v ref = ? .5v 730 1 ? 50 a ocp comparator i comp co ? pa ? ato ? ope ? ating cu ?? ent 5v no load 30 ? 0 a v cmpos co ? pa ? ato ? input offset voltage 5v -15 15 ? v 5v by ? ali ?? ation - ? ? ? v v hys co ? pa ? ato ? hyste ? esis width 5v ? 0 ? 0 ? 0 ? v v cm co ? pa ? ato ? co ?? on mode voltage range 5v v ss v dd - 1. ? v ocp opa i opa opa ope ? ating cu ?? ent 5v no load ? 00 350 a v opaos opa input offset voltage 5v -15 15 ? v with ? ali ?? ation - ? ? ? v v cm opa co ?? on mode voltage range 5v v ss v dd - 1. ? v gain opa gain e ?? o ? 5v a ll ? onditions -5 g 5 % dac for ocp i dac dac ope ? ating cu ?? ent 5v v ref = ? .5v ? 50 300 a 5v v ref =5v 500 ? 00 a r o r ? r output resisto ? 5v 10 k dnl dac diffe ? ential nonlinea ? ity -0.5 0.5 lsb inl dac integ ? al nonlinea ? ity -1 1 lsb power-on reset electrical characteristics ta = ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to e nsu ? e powe ? -on reset 100 ? v rr vdd v dd rising rate to e nsu ? e powe ? -on reset 0.035 v/ ? s t por mini ? u ? ti ? e fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ? s             
rev. 1.10 1? de?e??e? 1?? ?01? rev. 1.10 17 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the device take s advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal regis ters are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d c ontrol system with m aximum reliability a nd fexibility. t his makes t he device suitable for l ow- cost, high-volume production for controller applications. clocking and pipelining the m ain syst em c lock, de rived from e ither an hirc or l irc osc illator i s subdi vided i nto four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.                                                     
                   ?                   ?       ?  ?   ? system clock and pipelining for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications.
rev. 1.10 18 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 19 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu                           
      ? ? ? ?     ?  ? ? ?   ?                              ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc10~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jum ps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.10 18 de?e??e? 1?? ?01? rev. 1.10 19 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost.                        
                         arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation : rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement : inca, inc, deca, dec ? branch decision : jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu flash program memory the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number o f t imes, a llowing t he u ser t he c onvenience o f c ode m odification o n t he sa me d evice. by using the appropriate programming tools, th is flash device of fer s users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the progra m me mory ha s a c apacity of 2 k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.                         
  
   
  
   
    
   
   
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rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd[m] or t abrdl[m] instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.                            
                            
    instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrd [ ? ] @10 @9 @8 @7 @ ? @5 @ ? @3 @ ? @1 @0 tabrdl [ ? ] 1 1 1 @7 @ ? @5 @ ? @3 @ ? @1 @0 table location note: b10~b0 : t able location bits @7~@0: t able pointer (tblp) bits @10 ~@8: t able pointer (tbhp) bits
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?3 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 7 00h which refers to the start address of the last page within the 2 k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 7 06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address specifed by the tbhp and tblp registers if the t abrd [m] instruction is being used. the high byte of the table data which in t his case i s equal t o z ero wi ll b e t ransferred t o t he t blh register a utomatically wh en t he tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or specifc page mov a,0 7 h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address 7 06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address 7 05h transferred to tempreg2 and tblh ; in this example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2, the value 00h will be transferred to the high byte register tblh : : org 7 00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek write pins mcu programming pins function icpda pa 0 p ? og ? a ?? ing se ? ial data /add ? ess icpck pa ? p ? og ? a ?? ing se ? ial clo ? k vdd vdd powe ? supply vss vss g ? ound during the programming process, the user must there take care to ensure that no other outputs are connected to these two pins. the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for t he c lock. t wo a dditional l ines a re re quired for t he powe r suppl y. t he t echnical de tails regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature.                        
                        note: * may be resistor or capacito r. the resistance of * must be great er than 1k or the capacitance of * must be less than 1nf.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu on-chip debug support C ocds an ev chip exists for the purposes of device emulation. this ev chip device also provides an on-chip de bug fu nction t o de bug t he de vice du ring t he de velopment pr ocess. t he e v c hip and t he a ctual mc u de vices a re a lmost func tionally c ompatible e xcept for t he on-chip de bug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the actual mcu device will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for a more detailed ocds description, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on- ? hip de ? ug suppo ? t data /add ? ess input/output ocdsck ocdsck on- ? hip de ? ug suppo ? t clo ? k input vdd vdd powe ? supply gnd vss g ? ound
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections , the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h. 00h 7fh 80h ffh spe?ial pu?pose data me?o?y gene?al pu?pose data me?o?y eec at ?0h in bank 1 bank 0 data memory structure capacity banks 1 ? 8 8 bank 0: 80h~ffh general purpose data memory structure
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu 00h iar0 01h mp0 0?h iar1 03h mp1 0?h 05h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0ah status 0bh smod 0ch lvdc 0dh integ 0eh 0fh 10h intc0 11h intc1 1?h 19h papu 18h pawu 1bh 1ah 1dh 1ch 1fh pa pac 13h 1?h mfi0 15h mfi1 1?h 17h : unused? ?ead as 00h intc? mfi? pbc wdtc tbc pbpu pb ctrl sadol sadoh sadc0 sadc1 tm0dl tm0dh tm0al tm0ah cpr tm1c1 ?0h ?1h ??h ?9h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ?3h ??h ?5h ??h ?7h 30h 31h 3?h 3dh 3ch 3fh 3eh 33h 3?h 35h 3?h 37h tm1dl tm1dh tm1al tm1ah ocpc0 ?0h ?1h ??h ?3h ??h ?5h ??h ?7h ?8h ?9h ?ah 7fh bp unused lvrc tm1c0 tm1rpl tm1rph ocpda ocpocal ocpccal tm?dh unused : : mfi3 1eh eea eed bank 0? 1 bank 0 bank 1 eec ocpc1 tm?c0 tm?c1 tm?dl unused tm0rpl tm0rph ctrl? ctrl3 ctrl? ctrl5 38h 39h 3ah 3bh tm?rph tm?al tm?ah tm?rpl ?bh ?ch ?dh tm0c0 tm0c1 ?eh unused unused special purpose data memory structure
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu special function register description most of the special function register details will be described in the relevant functional section. however, several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org00h start : mov a , 04h ; setup size of block mov block , a mov a , offset adres1 ; accumulator loaded with frst ram address mov mp0 , a ; setup memory pointer with frst ram address loop : clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu bank pointer C bp for this device, the data memory is divided into two banks , bank0 and bank1 . selecting the required data memory area is achieved using the bank pointer . bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addre ssing the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from bank 1 must be implemented using indirect a ddressing. bp register bit 7 6 5 4 3 2 1 0 na ? e dmbp0 r/w r/w por 0 b it 7 ~ 1 unimplemented, read as 0 b it 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user - defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter s a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.10 30 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 31 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu status register bit 7 6 5 4 3 2 1 0 na ? e to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 unknown b it 7 ~ 6 unimplemented, read as 0 b it 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. b it 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction b it 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. b it 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero b it 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction b it 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.10 30 de?e??e? 1?? ?01? rev. 1.10 31 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu eeprom data memory one of the s pecial features in the device is its internal eep rom d ata m emory. eep rom, w hich stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory , with data retention even when its power supply is removed. by incorporating this kind of data mem ory, a whol e new host of appl ication possibi lities are ma de avail able to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is up to 648 bits. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special function register . the eec register however , being located in bank 1, cannot be directly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d5 d ? d3 d ? d1 d0 eed d7 d ? d5 d ? d3 d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 na ? e d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 ~ 6 unimplemented, read as 0 b it 5 ~ 0 data eeprom address data eeprom address bit 5 ~ bit 0
rev. 1.10 3 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 33 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu eed register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 eeprom data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 na ? e wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 4 unimplemented, read as 0 b it 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. b it 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. b it 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. b it 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.10 3? de?e??e? 1?? ?01? rev. 1.10 33 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom to write data to the eeprom, the eeprom address of the data to be written must frst be placed in t he ee a regist er and t he dat a pla ced in t he ee d regist er. then t he writ e enabl e bit , wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the e ec r egister m ust be i mmediately se t hi gh t o i nitiate a wri te c ycle. t hese t wo i nstructions must be executed consecutively . the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the applic ation program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
rev. 1.10 3 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 35 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic b y e nsuring t hat t he w rite e nable b it i s n ormally c leared t o z ero wh en n ot wr iting. al so the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the devic e should not enter the idle or sleep mode until the eeprom read or write operation is totally completed, otherwise, the eeprom read or write operation will fail. programming examples ? reading data from the eeprom C polling method mov a , eeprom_adres ; user defned address mov e ea, a mov a , 040h ; setup memory pointer mp1 mov m p1, a ; mp1 points to eec register mov a , 01h ; setup bank pointer mov b p, a set i ar1.1 ; set rden bit, enable read operations set i ar1.0 ; start read cycle - set rd bit back: sz i ar1.0 ; check for read cycle end jmp b ack clr iar1 ; disable eeprom read/write clr bp mov a , eed ; move read data to register mov r ead_data, a ? writing data to the eeprom C polling method mov a , eeprom_adres ; user defned address mov e ea, a mov a , eeprom_data ; user defned data mov e ed, a mov a , 040h ; setup memory pointer mp1 mov m p1, a ; mp1 points to eec register mov a , 01h ; setup bank pointer mov b p, a ; bp points to data memory bank 1 clr e mi set i ar1.3 ; set wren bit, enable write operations set i ar1.2 ; start write cycle - set wr bit C executed immediately ; after set wren bit set e mi back: sz i ar1.2 ; check for write cycle end jmp b ack clr iar1 ; disable eeprom read/write clr bp
rev. 1.10 3? de?e??e? 1?? ?01? rev. 1.10 35 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for the watchdog t imer and t ime base interrupts. f ully integrated inte rnal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillators p rovide h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capabilit y of dynamically switching between fast and slow system clock, the device has the fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. inte ? nal high speed rc hirc 1 ? /1 ? / ? 0mhz inte ? nal low speed rc lirc 3 ? khz oscillator types system clock confgurations there are t wo m ethods of generat ing t he syst em cl ock, a high spee d osci llator and a low spee d oscillator. t he h igh sp eed o scillator is t he i nternal 12mhz, 1 6mhz o r 2 0 mhz rc o scillator. t he low speed oscillator is the internal 32khz rc oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register . note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no- oscillator selection for either the high or low speed oscillator. high speed os?illato? hirc lirc low speed os?illato? f h ? - stage p ?es?ale? hlclk ? cks ? ~ cks0 ?its f h / ? f h / ? f h /8 f h /1 ? f h /3 ? f h / ?? f sub f sys system clock confgurations
rev. 1.10 3 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 37 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fxed frequencies of either 12mhz, 16mhz or 2 0mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. note that if this internal system clock option is selected, as it requires no external pins for its operation . internal 32khz oscillator C lirc the internal 32khz system oscillator is the low frequency oscillator . it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency , f h , or low frequency , f sub , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock can be sourced from the hirc oscillator . the low speed system clock source can be sourced from the lirc osc illator. t he ot her c hoice, wh ich i s a di vided ve rsion of t he hi gh sp eed system oscillator has a range of f h /2~f h /64.
rev. 1.10 3? de?e??e? 1?? ?01? rev. 1.10 37 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu                
        
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 system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. system operation modes there a re five d ifferent m odes o f o peration f or t he m icrocontroller, e ach o ne wi th i ts o wn special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep , idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operating mode description cpu f sys f sub f tbc normal ? ode on f h ~f h / ?? on on slow ? ode on f sub on on ilde0 ? ode off off on on idle1 ? ode off on on on sleep ? ode off off on off
rev. 1.10 38 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 39 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the high speed oscillator , hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod regis ter. a lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock so urce. t he c lock so urce u sed wi ll b e f rom f sub . r unning t he m icrocontroller i n t his m ode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep mode the cpu will be stopped. however the f s ub clock will continue to operate . idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl register i s l ow. in t he idle 0 mode t he system oscillator will be inhibited from driving the cpu, the system oscillator will be stopped, the low frequency clock f sub will be on. idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator . in the idle1 mode the low frequency clock f sub will be on. note: if l vden=1 and the sleep or idle mode is entered, the l vd and bandgap functions will not be disabled, and the f sub clock will be forced to be enabled .
rev. 1.10 38 de?e??e? 1?? ?01? rev. 1.10 39 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu control register the smod register is used to control the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 na ? e cks ? cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 1 1 0 0 0 1 0 b it 7 ~ 5 cks2 ~ cks0 : the system clock selection when hlclk is 0 000: f sub 001: f sub 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0 b it 3 lto : lirc system osc sst ready fag 0: not ready 1: ready this is the low speed system oscillator sst ready fag which indicate s when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will change to a high level after 1~2 cycles. b it 2 hto : hirc system osc sst ready fag 0: not ready 1: ready this is the high speed system oscill ator sst ready fag which indicates when the high speed system oscillator is stable after a wake-up has occurred. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the h igh sp eed sy stem o scillator i s stable. t herefore t his fag wi ll a lways b e r ead a s 1 by the application program after device power -on. the fag will be low when in the sleep or idle 0 mode but after power on reset or a wake-up has occurred, the fag will change to a high level after 15~16 clock cycles if the hirc oscillator is used. b it 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he idle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o keep t he pe ripheral fun ctions ope rational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. b it 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f sub clock will be selected. when system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched off to conserve power.
rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu ctrl register bit 7 6 5 4 3 2 1 0 na ? e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x" unknown b it 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as 0 b it 2 lvrf : lvr function reset fag describe elsewhere b it 1 lrf : lvrc control register software reset fag describe elsewhere b it 0 wrf : wdt control register software reset fag describe elsewhere                                     
   
 
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rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction . when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condit ion of the idl en bit in the smod regi ster and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal cloc k sources will also stop running, which may af fect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when the device moves between the various operating modes. normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se t ting t he hlclk bit to 0 and set ting the cks2~cks0 bits to 000 or 001 in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.                           
                      ?? ?      ??       ? ? ?        ?? ?     ??       ? ? ?        ?? ?      ??  
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?3 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator . t o switch back to the normal mode, w here the high s peed s ystem os cillator is us ed, the h lclk bit s hould be s et to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked.                         
                         ? ? ??     ????      ? ?       ? ? ??     ????      ? ?       ? ? ??     ???? entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the hal t instruction in the application program with the idlen bit in smod register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruc - tion, but the t ime base clock f tbc and the low frequency f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock and f tbc and the low frequency f sub will be on and the ap - plication program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting . ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. t hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps .
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow i f the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. t he actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a sys tem power -up or executing the clear w atchdog t imer instructions and is set w hen executing the hal t instruction. the t o fag is set if a wdt time-out occurs, and causes a wake- up that only resets the program counter and stack pointer , the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal f sub clock which is in turn supplied by the lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 t o 2 18 t o gi ve l onger t imeouts, t he a ctual va lue be ing c hosen usi ng t he w s2~ws0 bi ts i n t he w dtc register. the lirc internal oscillato r has an approximate period of 32khz at a supply voltage of 5v . however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable operation . the wdtc register is initiated to 0101001 1b at any res et but keeps unchanged at the wd t time-out occurrence in a power down state. wdtc register bit 7 6 5 4 3 2 1 0 na ? e we ? we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~ 3 we4 ~ we0 : wdt enable bit 10101 or 01010: enabled others : reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set high. bit 2~ 0 ws2 ~ ws0 : select wdt t imeout period 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu ctrl register bit 7 6 5 4 3 2 1 0 na ? e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x" unknown b it 7 fsyson : f sys control idle mode describe elsewhere bit 6 ~ 3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag describe elsewhere bit 1 lrf: lvr control register software reset fag describe elsewhere bit 0 wrf: wdt control register software reset fag 0: not occur 1: occurred this bit is set high by the w dt control register software reset and cleared by the application program. note that this bit can only be cleared to zero by the application program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknow n location, or enters an endles s loop, these clear ins tructions w ill not be executed in the correct manne r, in which case the w atchdog t imer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to of fer enable and reset control of the w atchdog t imer. when the we4~we0 bits value are equal to 01010b or 10101b, the wdt function is enabled. however, if the we4~we0 bits are changed to any other values excep t 01010b and 10101b, which could be caused by adverse environmental conditions such as noise, it will reset the microcontroller after 2~3 lirc clock cycles. we4 ~ we0 bits wdt function 01010b o ? 10101b ena ? le any othe ? value reset mcu watchdog timer enable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value is written into the we4~we0 bit fled except 01010b a nd 10101b, t he se cond i s usi ng t he w atchdog t imer soft ware c lear i nstructions a nd t he third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu clr wdtinst?u?tion 8-stage divide? wdt p?es?ale? we?~we0 ?its wdtc registe? reset mcu f sub /? 8 8-to-1 mux clr ws?~ws0 wdt ti?e-out (? 8 /f sub ~ ? 18 /f sub ) lirc haltinst?u?tion f sub watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the watchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a microcontroller reset can occur, through events occurring internally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. vdd powe?-on reset sst ti?e-out t rstd 1rwh w 5?7' lv srzhurq ghod wslfdo wlph pv power-on reset timing chart
rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu low voltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device . the l vr function is always enabled with a specifc l vr voltag e, v lvr . if the supply voltage of the device drops to within a range of 0.9v~ v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set high . f or a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specified in the lvd&lvr characteristics. if the low voltage sta te doe s not e xceed this va lue , t he l vr wil l i gnore the l ow suppl y vol tage a nd wi ll not perform a reset function. the actual v lvr is defned by the l vs7~lvs0 bits in the l vrc register . if the l vs7~lvs0 bits are changed to any other value except some certain values defined in the l vrc register by the environmental noise, the l vr will reset the device after 2~3 lirc cloc k cycles. when this happens, the lrf bit in the ctrl register will be set high . after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode.                 note:t rstd is power-on delay, typical time=50ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 na ? e lvs7 lvs ? lvs5 lvs ? lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r r r/w r/w por 0 1 0 1 0 1 0 1 b it 7 ~ 0 lvs7 ~ lvs0 : lvr v oltage select control 01010101: 2. 1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other value: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles. in thi s situation thi s register contents will remain the same after such a reset occurs. any register value, other than the defined value s above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation this register contents will be reset to the por value.
rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu ? ctrl register bit 7 6 5 4 3 2 1 0 na ? e fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x" unknown b it 7 fsyson : f sys control idle mode describe elsewhere bit 6 ~ 3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set high when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to zero by the application program. bit 1 lrf: lvr control register software reset fag 0: not occur 1: occurred this bit is set high if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to zero by the application program. bit 0 wrf: wdt control register software reset fag describe elsewhere watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a lvr reset except that the watchdog time-out fag t o will be set high.                    note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cleared to zero and the t o fag will be set high . refer to the a.c. characteristics for t sst details.               wdt time-out reset during sleep or idle timing chart
rev. 1.10 50 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 51 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu reset initial conditions the dif ferent types of res et des cribed af fect the res et fags in dif ferent w ays. thes e fags , know n as pdf and t o are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or w atchdog t imer. the reset flags are shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset u u lvr ? eset du ? ing normal o ? slow mode ope ? ation 1 u wdt ti ? e-out ? eset du ? ing normal o ? slow mode ope ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? sleep mode ope ? ation note: u stands for unchanged the following table indicates the w ay in w hich the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? a ? counte ? reset to ze ? o inte ?? upts all inte ?? upts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins ? ounting ti ? e ? modules ti ? e ? modules will ? e tu ? ned off input/output po ? ts i/o po ? ts will ? e setup as inputs sta ? k pointe ? sta ? k pointe ? will point to the top of the sta ? k the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know wh at c ondition t he m icrocontroller i s i n a fter a p articular r eset o ccurs. t he f ollowing t able describes how each type of reset affects each of the microcontroller internal registers. register reset (power on) wdt time-out (normal operation) wdt time-out (sleep/idle ) p ? og ? a ? counte ? 000h 000h 000h mp0 xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx uuuu uuuu bp ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu tbhp ---- -xxx ---- -uuu ---- -uuu status --00 xxxx --1u uuuu --11 uuuu smod 110- 0010 110- 0010 uuu- uuuu lvdc --00 -000 --00 -000 --uu -uuu integ ---- 0000 ---- 0000 ---- uuuu intc0 -00- 00-0 -00- 00-0 -uu- uu-u intc1 0000 0000 0000 0000 uuuu uuuu intc ? 0000 0000 0000 0000 uuuu uuuu mfi0 --00 --00 --00 --00 --uu --uu mfi1 --00 --00 --00 --00 --uu --uu mfi ? --00 --00 --00 --00 --uu --uu
rev. 1.10 50 de?e??e? 1?? ?01? rev. 1.10 51 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu register reset (power on) wdt time-out (normal operation) wdt time-out (sleep/idle ) mfi3 --00 --00 --00 --00 --uu --uu pa 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 uuuu uuuu pb ---- 1111 ---- 1111 ---- uuuu pbc ---- 1111 ---- 1111 ---- uuuu pbpu ---- 0000 ---- 0000 ---- uuuu wdtc 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 uuuu -uuu eea --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- uuuu sadol (adrfs=0) xxxx ---- xxxx ---- uuuu ---- sadoh (adrfs=0) xxxx xxxx xxxx xxxx uuuu uuuu sadol (adrfs=1) xxxx xxxx xxxx xxxx uuuu uuuu sadoh (adrfs=1) ---- xxxx ---- xxxx ---- uuuu sadc0 0000 0000 0000 0000 uuuu uuuu sadc1 0000 0000 0000 0000 uuuu uuuu ctrl 0--- -x00 0--- -000 u--- -uuu lvrc 0101 0101 0101 0101 uuuu uuuu tm0c0 0000 0--- 0000 0--- uuuu u--- tm0c1 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 uuuu uuuu tm0dh ---- -- 00 ---- -- 00 ---- -- uu tm0al 0000 0000 0000 0000 uuuu uuuu tm0ah ---- -- 00 ---- -- 00 ---- -- uu tm0rpl 0000 0000 0000 0000 uuuu uuuu tm0rph ---- --00 ---- --00 ---- --uu tm1c0 0000 0--- 0000 0--- uuuu u--- tm1c1 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --uu tm1rpl 0000 0000 0000 0000 uuuu uuuu tm1rph ---- --00 ---- --00 ---- --uu cpr 1000 0000 1000 0000 1uuu uuuu ocpc0 0000 ---0 0000 ---0 uuuu ---u ocpc1 --00 0000 --00 0000 --uu uuuu ocpda 0000 0000 0000 0000 uuuu uuuu ocpocal 0000 0000 0000 0000 uuuu uuuu
rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 53 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu register reset (power on) wdt time-out (normal operation) wdt time-out (sleep/idle ) ocpccal 0001 0000 0001 0000 uuuu uuuu ctrl ? 0-00 0001 0-00 0001 u-uu uuuu ctrl3 0000 0000 0000 0000 uuuu uuuu ctrl ? ---0 0000 ---0 0000 ---u uuuu ctrl5 -000 0000 -000 0000 -uuu uuuu tm ? c0 0000 0--- 0000 0--- uuuu u--- tm ? c1 0000 0000 0000 0000 uuuu uuuu tm ? dl 0000 0000 0000 0000 uuuu uuuu tm ? dh ---- --00 ---- --00 ---- --uu tm ? al 0000 0000 0000 0000 uuuu uuuu tm ? ah ---- --00 ---- --00 ---- --uu tm ? rpl 0000 0000 0000 0000 uuuu uuuu tm ? rph ---- --00 ---- --00 ---- --uu note: "-" not implement "u" stands for "unchanged" "x" stands for "unknown"
rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 53 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a ~ p b . these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa pa7 pa ? pa5 pa ? pa3 pa ? pa1 pa0 pac pac7 pac ? pac5 pac ? pac3 pac ? pac1 pac0 papu papu7 papu ? papu5 papu ? papu3 papu ? papu1 papu0 pawu pawu7 pawu ? pawu5 pawu ? pawu3 pawu ? pawu1 pawu0 pb pb3 pb ? pb1 pb0 pbc pbc3 pbc ? pbc1 pbc0 pbpu pbpu3 pbpu ? pbpu1 pbpu0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using registers papu~p b pu, and are implemented using weak pmos transistors. note that only when the i/o ports are confgured as digital intput or nmos output, the internal pull- high f unctions c an b e e nabled u sing t he p apu~pbpu r egisters. i n o ther c onditions, i nternal p ull- high functions are disabled. papu register bit 7 6 5 4 3 2 1 0 na ? e papu7 papu ? papu 5 papu ? papu 3 papu ? papu1 papu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 i/o port a bit7~ bit 0 pull-high control 0: disable 1: enable pbpu register bit 7 6 5 4 3 2 1 0 na ? e pbpu3 pbpu ? pbpu1 pbpu0 r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 4 unimplemented, read as 0 b it 3 ~ 0 i/o port b bit 3 ~ bit 0 pull-high control 0: disable 1: enable
rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 55 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. note that only when the port a pins are confgured as general purpose i/os and the device is in the halt s tatus, the p ort a w ake-up functions can be enabled us ing the relevant bits in the p awu register. in other conditions, the wake-up function s are disabled. pawu register bit 7 6 5 4 3 2 1 0 na ? e pawu7 pawu ? pawu5 pawu ? pawu3 pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 i/o port a bit 7 ~ bit 0 w ake up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac~p b c, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 na ? e pac7 pac ? pac5 pac ? pac3 pac ? pac1 pac0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 input/output control 0: output 1: input pbc register bit 7 6 5 4 3 2 1 0 na ? e pbc3 pbc ? pbc1 pbc0 r/w r/w r/w r/w r/w por 1 1 1 1 bit 7~4 unimplemented, read as 0 bit 3~0 i/o port b bit 3~bit 0 input/output control 0: output 1: input
rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 55 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for these pins, the desired function of the multi-function i/o pins is selected by a series of registers via the application program control. pin-shared function selection registers the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. the device include s the ctrl3 and ctrl4 register s which can select the desired functions of the multi-function pin-shared pins . the m ost i mportant p oint t o n ote i s t o m ake sur e t hat t he d esired p in-shared f unction i s p roperly selected and also deselected. t o select the desired pin-shared function, the pin-shared function should frst be correctly selected using the corresponding pin-shared control register . after that the corresponding peripheral functional setting should be confgured and then the peripheral function can be enabled. t o correctly desele ct the pn-shared function, the peripheral function should frst be disabled and then the corresponding pin-shared function control register can be modifed to select other pin-shared functions. pin-shared function selection registers list name bit 7 6 5 4 3 2 1 0 ctrl3 iocn7 iocn ? iocn5 iocn ? iocn3 iocn ? iocn1 iocn0 ctrl ? iocn1 ? iocn11 iocn10 iocn9 iocn8 ctrl3 register bit 7 6 5 4 3 2 1 0 na ? e iocn7 iocn ? iocn5 iocn ? iocn3 iocn ? iocn1 iocn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 iocn7~iocn6 : pa5 pin function selection 0 0: int1/tck1/pa5 0 1: an3 10: ocp1 11: int1/tck1/pa5 the int1 or tck1 pin is furtherly selected using the corresponding function selection bits in the interrupt control register or tm control register. bit 5~4 iocn5~iocn4 : pa4 pin function selection 0 0: pa4 0 1: an2 10: tp1 11: pa4 bit 3~2 iocn3~iocn2 : pa3 pin function selection 0 0: int0/tck0/pa3 0 1: an1 10: vref 11: int0/tck0/pa3 the int0 or tck0 pin is furtherly selected using the corresponding function selection bits in the interrupt control register or tm control register.
rev. 1.10 5 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 57 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu bit 1~0 iocn1~iocn0 : pa1 pin function selection 0 0: pa1 0 1: an0 10: tp0 11: pa1 ctrl4 register bit 7 6 5 4 3 2 1 0 na ? e iocn1 ? iocn11 iocn10 iocn9 iocn8 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4 iocn12 : pb0 pin function selection 0: pb0 1: pwm0h bit 3~2 iocn11~iocn10 : pa7 pin function selection 0 0: tck2/pa7 0 1: an5 10: pwm0l 11: tck2/p a7 the tck2 pin is furtherly selected using the corresponding function selection bits in the tm control register. bit 1~0 iocn9~iocn8 : pa6 pin function selection 0 0: pa6 0 1: an4 10: ocp0 11: tp2 i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.                    
                                           
                       ???     ??     ?   ?  ?          generic input/output structure
rev. 1.10 5? de?e??e? 1?? ?01? rev. 1.10 57 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu                        
                         
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 ?  ?          ?   ? -  ?  ? -  ?  ? ?        ? a/d input/output structure programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~p b c, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a~p b , are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming individual b its i n t he p ort c ontrol r egister u sing t he set [ m].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.                         
       read/wite timing port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.10 58 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 59 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu timer modules C tm one of the most fundamental functions in any microcont roller device is the ability to control and measure time. t o implement time related functions the device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. introduction the devic e contai n s three 10-bit periodic tms, each tm having a reference name of tm0 , tm 1 and tm2 . the main features of the tms are summarised in the accompanying table. function ptm ti ? e ? /counte ? i/p captu ? e co ? pa ? e mat ? h output pwm channels 1 single pulse output 1 pwm align ? ent edge pwm adjust ? ent pe ? iod & duty duty o ? pe ? iod tm function summary tm0 tm1 tm2 10- ? it ptm 10- ? it ptm 10- ? it ptm tm name/type reference tm operation the t m s of fer a di verse ra nge of func tions, from si mple t iming ope rations t o pw m si gnal generation. t he k ey t o u nderstanding h ow t he t m o perates i s t o se e i t i n t erms o f a f ree r unning counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator , known as a compare match s ituation, a tm interrupt s ignal w ill be generated w hich can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts each periodic tms ha s two internal interrupts, the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin.
rev. 1.10 58 de?e??e? 1?? ?01? rev. 1.10 59 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tms each ha ve one output pin which is selected using the corresponding pin-shared function selection bits described in the pin-shared function section . when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using relevant pin-shared function selection register. type tm0 tm1 tm2 pin control registers input tck0 tck1 tck ? ctrl3 o ? ctrl ? output tp0 tp1 tp ? ctrl3 o ? ctrl ? tm external pins tm input/output pin control selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using t he r elevant p in-shared f unction se lection r egister s , wi th the c orresponding se lection b it s i n each pin-shared function register corresponding to a tm input/output pin. confguring the selection bit s correctly will setup the corresponding pin as a tm input/output . the details of the pin-shared function selection are described in the pin-shared function section. tm0 (ptm) tp0 tck0 tp output tck input iocn1~iocn0 iocn3~iocn? 0 1 t0capts captu?e input tm 0 function pin control block diagram tm1 (ptm) tp1 tck1 tp output tck input iocn5~iocn? iocn7~iocn? 0 1 t1capts captu?e input tm 1 fun?tion pin cont?ol blo?k diag?a?
rev. 1.10 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?1 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu tm2 (ptm) tp? tck? tp output tck input iocn9~iocn8 iocn11~iocn10 0 1 t?capts captu?e input tm 2 function pin control block diagram programming considerations the t m c ounter r egisters , t he c apture/compare c cra and the c crp r egisters, b eing 1 0 -bit, a ll have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buffer and its rela ted low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra or ccrp low byte registers, named tm n al or tm n rpl, using the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values. data bus 8-?it buffe? tmndh tmndl tmnrph tmnrpl tmnah tmnal tm counte? registe? (read only) tm ccra registe? (read/w?ite) tm ccrp registe? (read/w?ite) 7kh iroorzlqj vwhsv vkrz wkh uhdg dqg zulwh surfhgxuhv :ulwlqj 'dwd wr &&5 ru &&5 p ? step 1. w rite data to low byte tm n al or tm nrp l C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tm n ah or tm nrp h C here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccr a or ccr p ? step 1. read data from the high byte tm n dh, tm n ah or tm nrp h C here d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tm n dl, tm n al or tm nrp l C this step reads data from the 8-bit buffer.
rev. 1.10 ?0 de?e??e? 1?? ?01? rev. 1.10 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu periodic type tm C ptm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can also be controlled with an external input pin and can drive one external output pin. periodic tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with the ccra and ccrp registers. the onl y way of changi ng the value of the 10-bit count er using the appl ication program , is to clear the counter by changing the t n on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pin. all operating setup conditions are selected using relevant internal registers.                         
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     ?    
                     ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ?  ? ?      ?   periodic type tm block diagram (n=0~2)
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?3 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu periodic type tm register description overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccr p value. the remaining two registers are control registers which setup the different operating and control modes . name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tn pau tn ck ? tnck1 tnck0 tnon tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr tmndl d7 d ? d5 d ? d3 d ? d1 d0 tmndh d9 d8 tmnal d7 d ? d5 d ? d3 d ? d1 d0 tmnah d9 d8 tmnrpl d7 d ? d5 d ? d3 d ? d1 d0 tmnrph d9 d8 10-bit periodic tm register list (n=0~2) tmnc0 register bit 7 6 5 4 3 2 1 0 na ? e tn pau tn ck ? tnck1 tnck0 tnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7 tn pau : tm n counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. b it 6 ~ 4 t n ck2 ~ tnck0 : select tm n counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: f h 110: tck n rising edge clock 111: tck n falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f sys is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. b it 3 t non : tm n counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tm output control bit, when the bit changes from low to high. b it 2 ~ 0 uni mplemented, read as 0
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu tmnc1 register bit 7 6 5 4 3 2 1 0 na ? e tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 6 t nm1~tnm0 : select tm n operat ion mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. b it 5 ~ 4 t nio1~tnio0 : select tp n output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp n 01: input capture at falling edge of tp n 10: input capture at falling/rising edge of tp n 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the se bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit. note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t n on bit from low to high. in the pwm mode, the t n io1 and t n io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by changing t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the t n io1 and t n io0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t n io1 and t n io0 bits are changed when the tm is running.
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?5 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu b it 3 t noc : tp n output control bit compare match output mode 0: i nitial low 1: i nitial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. b it 2 t npol : tp n output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp n output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. b it 1 t ncapts : tm n capture trigger source select 0: from tp n pin 1: from tck n pin b it 0 t ncclr : select tm n counter clear condition 0: tm n comparatror p match 1: tm n comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains two c omparators, com parator a and com parator p , e ither of which can be selected to clear the internal counter . w ith the t n cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t n cclr bit is not used in the pwm, single pulse or input capture mode. tmn dl register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~ 0 tm ndl : tm n counter low byte register bit 7 ~ bit 0 tmn 1 0 -bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r r por 0 0 b it 7 ~ 2 unimplemented, read as 0 b it 1 ~ 0 tmndh : tm n counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu tmn al register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 tm nal : tm n ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r/w r/w por 0 0 b it 7 ~ 2 unimplemented, read as 0 b it 1 ~ 0 tmnah : tm n ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 tmnrp l register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 tm nrpl : tm n ccr p low byte register bit 7 ~ bit 0 tmn 10-bit ccr p bit 7 ~ bit 0 tmnrph register bit 7 6 5 4 3 2 1 0 na ? e d9 d8 r/w r/w r/w por 0 0 b it 7 ~ 2 unimplemented, read as 0 b it 1 ~ 0 tmnrph : tm n ccr p high byte register bit 1 ~ bit 0 tmn 10-bit ccr p bit 9 ~ bit 8
rev. 1.10 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?7 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu periodic type tm operating modes the periodic t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the t n m1 and t n m0 bits in the tm n c1 register. compare match output mode to se lect t his m ode, b its t n m1 a nd t n m0 i n t he t m n c1 r egister , sh ould b e a ll c leared t o 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the t n cclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both the t n af and t n pf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the t n cclr bit in the tm n c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t n af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t n cclr i s h igh n o t n pf i nterrupt r equest fa g wi ll b e g enerated. in t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t n af interrupt request fag is ge nerated a fter a c ompare m atch oc curs fro m co mparator a. t he t n pf i nterrupt re quest fl ag, generated from a compare match from comparator p , will have no ef fect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the t n io1 and tn io0 bits in the tm n c1 register . the tm output pin can be selected using the t nio1 and tn io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the t n on bit changes from low to high, is setup using the t n oc bit. note that if the t nio1, tn io0 bits are zero then no pin change will take place.
rev. 1.10 ?? de?e??e? 1?? ?01? rev. 1.10 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu counte? value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin ti?e ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 a?tive high output sele?t he?e tnio [1:0] = 11 toggle output sele?t output not affe?ted ?y tnaf flag. re?ains high until ?eset ?y tnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when tnpol is high compare match output mode C tncclr = 0 note: 1. w ith t n cclr = 0 -- a comparator p match will clear the counter 2. the tm output pin is controlled only by the tn af fag 3. the o utput pin is reset to initial state by a tn on bit rising edge 4. n=0~2
rev. 1.10 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 ?9 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu counte? value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin ti?e ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resu?e stop counte? resta?t tncclr = 1; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 a?tive high output sele?t he?e tnio [1:0] = 11 toggle output sele?t output not affe?ted ?y tnaf flag. re?ains high until ?eset ?y tnon ?it output pin reset to initial value output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when tnpol is high tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow output does not ?hange compare match output mode C tncclr = 1 note: 1. w ith t n cclr = 1 -- a comparator a match will clear the counter 2. the tm output pin is controlled only by the tn af fag 3. the output pin is reset to initial state by a tn on rising edge 4. the tn pf fag is not generated when t n cclr = 1 5. n=0~2
rev. 1.10 ?8 de?e??e? 1?? ?01? rev. 1.10 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu timer/counter mode to select this mode, bits t nm1 and tn m0 in the tm n c1 register should all be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to se lect t his mode , bits t n m1 and t n m0 in t he t mnc1 regi ster should be se t t o 10 respe ctively and also the t n io1 and t n io0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t n cclr bi t ha s no e ffect a s t he pw m period . both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycl e. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t n oc bit in the tm n c1 register is used to select the required polarity of the pwm waveform while the two t n io1 and t n io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t n pol bit is used to reverse the polarity of the pwm output waveform. 10-bit ptm, pwm mode period duty ccrp ccra if f h = 2 0mhz, tm clock source select f h , ccrp = 2 00 and ccra = 50, the tm pwm output frequency = (f h ) / 2 00 = 20mhz/2 00 = 100 khz, duty = 50/2 00 = 25% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.10 70 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 71 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tmn o/p pin (tnoc=1) ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? stop if tnon ?it low counte? reset when tnon ?etu?ns high tnm [1:0] = 10 pwm duty cy?le set ?y ccra pwm ?esu?es ope?ation output ?ont?olled ?y othe? pin-sha?ed fun?tion output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tmn o/p pin (tnoc=0) pwm mode note: 1. here c ounter cleared by ccrp 2. a counter clear sets the pwm period 3 . the i nternal pwm function continues running even when t n io[1:0] = 00 or 01 4 . the t n cclr bit has no infuence on pwm operation 5. n=0~2
rev. 1.10 70 de?e??e? 1?? ?01? rev. 1.10 71 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu single pulse output mode to se lect t his m ode, t he r equired b it p airs, t n m1 a nd t n m0 sh ould b e se t t o 1 0 r espectively a nd a lso the corresponding t nio1 and t n io0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the t n on bit, which can be implemented using the application program. however in the single pulse mode, the t n on bit can also be made to automatically change from low to high using the external tck n pin, which will in turn initiate the single pulse output. when the t n on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the t n on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the t n on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the t n on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate tm interrupts. the counter can only be reset back to zero when the t n on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t n cclr bit is also not used.            
                         
            
?  ? ?     ?   ? ? ?   ?      ? ? ?   single pulse generation (n=0~2)
rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 73 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu counte? value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when tnon ?etu?ns high tnm [1:0] = 10 ; tnio [1:0] = 11 pulse width set ?y ccra output inve?ts when tnpol = 1 no ccrp inte??upts gene?ated tm o/p pin (tnoc=0) tckn pin softwa?e t?igge? clea?ed ?y ccra ?at?h tckn pin t?igge? auto. set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tck n pin or by setting the t n on bit high 4. a tck n pin active edge will automatically set the t n on bit high 5. in the single pulse mode, t n io [1:0] must be set to 11 and can not be changed. 6. n=0~2
rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 73 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu capture input mode to s elect this mode bits t n m1 and t n m0 in the tm n c1 regis ter s hould be s et to 01 respectively . this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tp n or tckn pin , selected by the t n capts bit in the tm nc1 register . the input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the t nio1 and tn io0 bits in the tm n c1 register . the counter is started when the t n on bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tp n or tckn pin the present value in the counter will be latched into the ccra register and a tm interrupt generated. irrespective of what events occur on the tp n or tckn pin the counter will continue to free run until the t n on bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the t nio1 and tn io0 bits can select the active trigger edge on the tp n or tckn pin to be a rising edge, falling edge or both edge types. if the t nio1 and tn io0 bits are both set high, then no capture operation will take place irrespective of what happens on the tp n or t ckn pin, however it must be noted that the counter will continue to run. as the tp n or tck n pin is pin shared with other functions, care must be taken if the tm n is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the t n cclr, t n oc and t n pol bits are not used in this mode.
rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 75 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu counte? value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value ti?e counte? ?lea?ed ?y ccrp pause resu?e counte? reset tnm [1:0] = 01 tm ?aptu?e pin tpn o? tckn xx counte? stop tnio [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode note: 1. t n m[1:0] = 01 and active edge set by the tn io[1:0] bits 2. a tm capture input pin active edge transfers counter value to ccra 3. the tn cclr bit is not used 4. no output function C t n oc and t n pol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero 6. n=0~2
rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 75 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. it also can convert the internal signals, such as the ocpao signal from the ocp function or dc to dc voltage from the series resistors , into a 12-bit digital value. the external or internal analog signal to be converted is determined by the sains2~sains0 bits together with the sacs3~sacs0 bits. note that when the internal analog signal is to be converted, the pi n-shared c ontrol bi ts shoul d a lso be prope rly c onfigured e xcept t he sains a nd sacs bi t fields. m ore detailed information about the a /d input s ignal is des cribed in the a /d converter control registers and a/d converter input signal sections respectively. the accompanyin g block diagram shows the internal structure of the a/d converter together with its associated registers. external input channel s a/d channel select bits input pins ? sacs3~sacs0 an0~an5 pin-sha?ed sele?tion ocpao signal sacs3~sacs0 sains?~sains0 a/d conve?te? start adbz enadc v ss a/d clo?k ? n (n=0~7) f sys sacks?~sacks0 v dd vref savrs1~savrs0 enadc sadol sadoh an0 an1 an5 a/d refe?en?e voltage a/d data registe?s se?ies ?esisto?s a/d converter structure
rev. 1.10 7 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 77 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu a/d converter register description overall opera tion of t he a/ d c onverter i s c ontrolled usi ng four regi sters. a rea d onl y regi ster pai r exists to store the a/d converter data 12-bit value. the remaining two registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 sadol (adrfs=0) d3 d ? d1 d0 sadol (adrfs=1) d7 d ? d5 d ? d3 d ? d1 d0 sadoh (adrfs=0) d11 d10 d9 d8 d7 d ? d5 d ? sadoh (adrfs=1) d11 d10 d9 d8 sadc0 start adbz enadc adrfs sacs3 sacs ? sacs1 sacs0 sadc1 sains ? sains1 sains0 savrs1 savrs0 sacks ? sacks1 sacks0 a/d converter registers list a/d converter data registers C sadol, sadoh as the device contains an internal 12-bit a/d converter , it requires two data registers to store the converted value. these are a high byte register , known as sadoh, and a low byte register , known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is ut ilised, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he adrfs bi t i n t he sadc0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. note that the a/d converter data register contents will be cleared to zero if the a/d converter is disabled. adrfs sadoh sadol 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d ? d5 d ? d3 d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d ? d5 d ? d3 d ? d1 d0 a/d converter data registers a/d converter control registers C sadc0, sadc1 to control the function and operatio n of the a/d converter , two control registers known as sadc0, sadc1 a re p rovided. t hese 8 -bit re gisters d efne fu nctions suc h a s t he se lection o f whi ch a nalog channel i s c onnected t o t he i nternal a/d c onverter, t he di gitised da ta form at, t he a/ d c lock source as well as controlling the start function and monitoring the a/d converter busy status. the sacs3~sacs0 bi ts i n t he sadc0 re gister a re use d t o de termine whi ch e xternal c hannel i nput i s selected to be converted. the sains2~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. if the sains2~sains0 bits are set to 000 or 011~111 , the external analog channel input is selected to be converted and the sacs3~sacs0 bits can determine which external channel is selected to be converted. if the sains2~sains0 bits are set to 001, the ocpao signal from the ocp function is selected to be converted. if the sains2~sains0 bits are set to 010 , the dc/ dc vo ltage of t he se ries re sistors i s se lected t o be c onverted. care m ust be t aken whe n the internal analog signal is selected to be converted. if the internal analog signal is selected to be converted, t he sacs3~sacs0 bi ts m ust be properly set t o select a foa ting st ate . ot herwise, t he external channel input will be connected together with the internal analog signal. this will result in unpredictable situations such as an irreversible damage.
rev. 1.10 7? de?e??e? 1?? ?01? rev. 1.10 77 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu sains [2:0] sacs [3:0] input signals description e x ? ept 001 and 010 0000~ 0101 an0~an5 exte ? nal pin analog input 0110~1111 floating 001 0110~1111 opa output ocpao signal f ? o ? the ocp fun ? tion 010 0110~1111 dc/dc voltage dc/dc voltage of the se ? ies ? esisto ? s a/d converter input signal selection sadc0 register register name bit 7 6 5 4 3 2 1 0 na ? e start adbz enadc adrfs sacs3 sacs ? sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 0 1 0: start an a/d conversion 0 1 : reset the a/d converter and clear the adbz fag to 0 1 0 : start the a/d conversion and set the adbz fag to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. bit 6 adbz : a/d converter busy fag 0: no a/d conversion is in progress 1: a/d conversion is in progress this read only fag is us ed to indicate w hether the a /d convers ion is in progress or not. when the st art bit is set fro m low to high and then to low again, the adbz fag will be set to 1 to indicate that the a/d conversion is initiated. the adbz fag will be cleared to 0 after the a/d conversion is complete. bit 5 en adc : a/d converter function enable control 0: disable 1: enable this bit controls the a/d internal function. this bit should be set to one to enable the a/d comverter . if the bit is set low , then the a/d converter will be switched of f reducing the device power consumption. when the a/d converter function is disabled, the contents of the a/d data register pair, sadoh and sadol, will be cleared to 0. bit 4 adrfs : a/d converter data format control 0: a/d converter data format sadoh = d[11:4]; sadol = d[3:0] 1: a/d converter data format sadoh = d[11:8]; sadol = d[7:0] this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d converter data register section. bit 3~0 sacs3~sacs0 : a/d converter external analog input channel select 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110~1111 : floating
rev. 1.10 78 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 79 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu sadc1 register register name bit 7 6 5 4 3 2 1 0 na ? e sains ? sains1 sains0 savrs1 savrs0 sacks ? sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~5 sains2~sains0 : a/d converter input signal select 000: external source C external analog channel input 001: internal source C ocpao signal from the ocp function 010: internal source C dc/dc voltage of the series resistors 011 ~111: external source C external analog channel input care must be taken if the sains2~sains0 bits are set to 001 or 010 to select the internal a nalog si gnal t o be c onverted. w hen t he i nternal a nalog si gnal i s se lected t o be convert ed, the sacs3~sacs0 bit s m ust be set to a value from 0110 to 1111 . otherwise, the external channel input will be connected together with the internal analog signal. this will result in unpredictable situations such as an irreversible damage. bit 4~3 savrs1~savrs0 : a/d converter reference voltage select 00: from vref pin 01: from vdd pin 1x: from vref pin bit 2~0 sacks2~sacks0 : a/d conversion clock source select 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: f sys /128 these bits are used to select the clock source for the a/d converter. a/d operation the st art bit is used to start the ad conversion. when the microcontroller sets this bit from low to high and then low again, an analo g to digital conversion cycle will be initiated. when the st art bit is brought from low to high but not low again, the a/d conversion will not be initiated. the adbz bi t i n t he sadc0 re gister i s use d t o i ndicate whe ther t he a nalog t o di gital c onversion process is in progress or not. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleared to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the interrupts are enabled, an internal interrupt signal will be generated. this a/d internal interrupt s ignal w ill direct the program f ow to the as sociated a /d internal interrupt address f or p rocessing. i f t he a/ d i nternal i nterrupt i s d isabled, t he m icrocontroller c an p oll t he adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. although the a/d clock source is de termined by the syst em clock f sys , and by bi ts sacks2~sadcks0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended range of permissible a/d clock period, t ad ck , is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the sacks2~sadcks0 bits should not be set to 000 or 1 1x. doing so wi ll g ive a/ d c lock p eriods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater than the maximum a/d clock period which may result in inaccurate a/d conversion values.
rev. 1.10 78 de?e??e? 1?? ?01? rev. 1.10 79 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu f sys a/d clock period (t adck ) sacks [2:0]= 000 (f sys ) sacks [2:0]= 001 (f sys /2) sacks [2:0]= 010 (f sys /4) sacks [2:0]= 011 (f sys /8) sacks [2:0]= 100 (f sys /16) sacks [2:0]= 101 (f sys /32) sacks [2:0]= 110 (f sys /64) sacks [2:0]= 111 (f sys /128) 1 mhz 1s 2s 4s 8s 16s * 32s * 64s * 128s * ? mhz 500ns 1s 2s 4s 8s 16s * 32s * 64s * ? mhz 250ns * 500ns 1s 2s 4s 8s 16s * 32s * 8 mhz 125ns * 250ns * 500ns 1s 2s 4s 8s 16s * 1 ? mhz 83ns * 167ns * 333ns * ?? 7ns 1.33s 2.67s 5.33s 10.67s * 1 ? mhz 62.5ns * 125ns * 250ns * 500ns 1s 2s 4s 8s ? 0 mhz 50ns * 100ns * 200ns * 400ns * 800ns 1.6s 3.2s 6.4s a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he enadc bit in the sadc0 register . this bit must be set high to power on the a/d converter . when the e nadc b it i s se t h igh t o p ower o n t he a/ d c onverter i nternal c ircuitry a c ertain d elay, a s indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by confguring the corresponding pin-shared control bits, if the enadc bit is high then some power will still be consumed. in power conscious applications it is therefore recom mended that the enadc is set low to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the sa vrs1 and sa vrs0 bits. when the sa vrs bit feld is set to 01, the a/d converter re ference vol tage wil l c ome from t he vdd pi n. otherwi se, i f t he sa vrs bi t fel d i s set to any other value except 01, the a/d converter reference voltage will come from the vref pin. as the vref pin is pin-shared with other functions, when the vref pin is selected as the reference voltage supply pin, the vref pin-shared function control bits should be properly configured to disable other pin functions. savrs [1:0] reference voltage description 00 v ref a/d conve ? te ? refe ? en ? e voltage ? o ? es f ? o ? vref pin 01 v dd a/d conve ? te ? refe ? en ? e voltage ? o ? es f ? o ? vdd pin 1x v ref a/d conve ? te ? refe ? en ? e voltage ? o ? es f ? o ? vref pin a/d converter reference voltage selection
rev. 1.10 80 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 81 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu a/d input pins all of the a /d analog input pins are pin-shared w ith the i/o pins as w ell as other functions . the corresponding pin-shared function selection bits for each pin in the ctrl3 and ctrl4 registers, determine whether the external pins are setup as a/d converter analog channel inputs or they have other functions. if the corresponding pin is setup to be an a/d converter analog channel input, the original pin functions w ill be dis abled. in this w ay, pins can be changed under program control to change t heir func tion be tween a/ d i nputs a nd ot her func tions. al l pul l-high re sistors, whi ch a re setup through register programming, will be automatically disconnecte d if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the port control register to enable the a/d input as when the relevant pin-shared function selection bits enable an a/d analog channel input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref . however, the reference voltage can also be supplied from the power supply pin, a choice which is made through the sa vrs1 and sa vrs0 bits in the sadc1 register. the analog input values must not be allowed to exceed the value of v ref . c onversion rate and timing diagram a com plete a/d conversi on contains two parts, dat a sampli ng and dat a conversi on. the dat a sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. t herefore a total of 16 a/ d clock cycles for an a/ d conversion which is defned as t adc are necessary. maximum single a/d conversion rate = a/d clock period / 16 the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck clock cycles where t adck is equal to the a/d clock period. enadc start adbz sacs[3:0] off on off on t on?st t ads a/d sa?pling ti?e t ads a/d sa?pling ti?e sta?t of a/d ?onve?sion sta?t of a/d ?onve? sion sta?t of a/d ?onve?sion end of a/d ?onve?sion end of a/d ?onve?sion t adc a/d ?onve?sion ti?e t adc a/d ?onve?sion ti?e t adc a/d ?onve?sion ti?e 0011b 0010b 0000b 0001b a/d ?hannel swit?h a/d conversion timing
rev. 1.10 80 de?e??e? 1?? ?01? rev. 1.10 81 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by properly programming the sacks2~sacks0 bits in the sadc1 register. ? step 2 enable the a/d converter by setting the enadc bit in the sadc0 register to one. ? step 3 select which signal is to be connec ted to the internal a/d converter by correctly confguring the sains2~sains0 bits select the external channel input to be converted, go to step 4. select the internal analog signal to be converted, go to step 5. ? step 4 if the a/d input signal comes from the external channel input selecting by confguring the sains bit feld, the corresponding pins should frst be confgured as a/d input function by confguring the releva nt pin-shared function control bits. the desired analog channel then should be selected by confguring the sacs bit feld. after this step, go to step 6. ? step 5 before the a/d input signal is selected to come from the internal analog signal by confguring the sains bit feld, the sacs bit feld must be frst confgured to a value from 01 10 to 1 111 to disconnect the external channel input. the desired internal analog signal then can be selected by confguring the sains bit feld. after this step, go to step 6. ? step 6 select the reference voltgage source by confguring the savrs1~savrs0 bits. ? step 7 select the a/d converter output data format by confguring the adrfs bit. ? step 8 if a/d conversion interrupt is used, the interrupt control registers must be correctly confgured to ensure the a/d interrupt function is active. the master interrupt bontrol bit, emi, and the a/d conversion interrupt control bit, ade, must both be set high in advance. ? step 9 the a/d conversion procedure can now be initialized by setting the st art bit from low to high and then low again. ? step 10 if a/ d conversi on i s i n progre ss, t he adbz fla g wi ll be se t high. aft er t he a/ d conversi on process is complete, the a dbz flag w ill go low and then the output data can be read from sadoh and sadol registers. note: when checking for the end of the conversion process, if the met hod of polling the adbz bit in the sadc0 register is used, the interrupt enable step above can be omitted.
rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 83 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing use d, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit enadc low in the sadc0 regist er. when thi s happens, the int ernal a/ d converter ci rcuits wi ll not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb = (v dd or v ref ) 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.               

 
 
  
  
 
 
 
 ?  ? ? ? ? ?  ??    ?   ?   
 ? ideal a/d transfer function
rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 83 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an adbz polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock set enadc mov a,0 1 h ; setup ctrl3 to confgure pin an0 mov ctrl3 ,a mov a,20h mov sadc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d : polling_eoc: sz adbz ; poll the sadc0 register adbz bit to detect end of a/d conversion jmp polling_eoc ; continue polling : mov a,sadol ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,sadoh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : jmp start_conversion ; start next a/d conversion
rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 85 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock set enadc mov a,0 1 h ; setup ctrl3 to confgure pin an0 mov ctrl3 ,a mov a,20h mov sadc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : adc_isr: ; adc interrupt service routine mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : mov a, sadol ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a, sadoh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 85 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu complementary pwm output the device provides a complementary output pair of signals which can be used as a pwm driver signal. the signal is sourced from the tm 0 output signal, tp 0 . for pmos type upper side driving, the pwm output is an active low signal while for nmos type lower side driving the pwm output is an active high signal. when these complementary pwm outputs are both used to drive the upper and low sides, the dead time generator must be enabled using the dten bit in the cpr register , and then a dead time, which is programmable using the dtpsc and dt bit felds in the cpr register , will be inserted to prevent excessive dc currents. the dead time will be inserted whenever the rising edge of the dead time generator input signal occurs. w ith a dead time ins ertion, the output signals experience a delay before being eventually sent out to the external power transistors. the pw m0h or pw m0l si gnal, c an be c ontrolled by t he pw mh or pw ml si gnals re pectively or remains at a certain level, these are determined by the dcpd_ctl1 and dcpd_ctl0 bits repectively. the pwm0h and pwm0l pins are pin-shared with other funcitons and can be selected as complementary pwm outputs by the revelant pin-shared control bits in the ctrl4 register. tp0 dead ti?e gene?ato? dtpsc [1:0] p?es?ale? f h a b dt [?:0] e c d pwmh pwml f d mux 0 0 1 dcpd_ctl0 pwm0l pwm0h dcpd_ctl1 mux 1 0 1 complementary pwm output block diagram tp0 a b c d e dead ti?e dead ti?e dead ti?e dead ti?e dead ti?e dead ti?e co?ple?enta?y pwm output wavefo??
rev. 1.10 8 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 87 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu cpr register bit 7 6 5 4 3 2 1 0 na ? e dten pwmhpol pwmlpol dtpsc1 dtpsc0 dt ? dt1 dt0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 0 0 0 b it 7 dten: dead time enable 0: disable 1: enable bit 6 pwmhpol: pwmh output polarity control 0: non-invert 1: invert bit 5 pwmlpol: pwml output polarity control 0: non-invert 1: invert b it 4 ~ 3 dtpsc1~dtpsc0: dead time prescaler division ratio select 00: f d =f h /1 01: f d =f h /2 10: f d =f h /4 11: f d =f h /8 b it 2 ~ 0 dt2~dt0: dead time select 000: dead time is [(1/f d )-(1/f h )] ~ (1/f d ) 001: dead time is [(2/f d )-(1/f h )] ~ (2/f d ) 010: dead time is [(3/f d )-(1/f h )] ~ (3/f d ) 011: dead time is [(4/f d )-(1/f h )] ~ (4/f d ) 100: dead time is [(5/f d )-(1/f h )] ~ (5/f d ) 101: dead time is [(6/f d )-(1/f h )] ~ (6/f d ) 110: dead time is [(7/f d )-(1/f h )] ~ (7/f d ) 111: dead time is [(8/f d )-(1/f h )] ~ (8/f d ) ctrl5 register bit 7 6 5 4 3 2 1 0 na ? e hv_s1 hv_s0 dcpd_ctl1 dcpd_ctl0 bz_s1 bz_s0 bz_ctl r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~5 hv_s1 ~hv_s0 : control signal type selection for hv_en described elsewhere. bit 4 dcpd_ctl1 : dc to dc pwup control 0: pwm0h always high and build-in m4 pmos always off 1: pwm0h signal from pwmh bit 3 dcpd_ctl0 : dc to dc pwdn control 0: pwm0l always low 1: pwm0l signal from pwml bit 2~1 bz_s1 ~bz_s0 : control signal type selection for buzzer_en described elsewhere. bit 0 bz_ctl : buzzer control described elsewhere.
rev. 1.10 8? de?e??e? 1?? ?01? rev. 1.10 87 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu over current protection the device includes an over current protection function which provides a protection mechanism for applications. t o prevent the battery char ge or load current from exceeding a specifc level, the current on the ocp 0 and ocp1 pin s and from the series resistors are converted to a relevant voltage level acc ording to the current value using the ocp operational amplifer . it is then compared with a reference voltage generated by an 8-bit d/a converter . when an over current event occurs, an ocp interrupt will be generated if the corresponding interrupt control is enabled. over current protection operation the ocp circuit is used to prevent the input current from exceeding a reference level. the current on the ocp 0 or ocp1 pin or from the series resistors is converted to a voltage and then amplifed by the ocp operational amplifer with a programmable gain from 1 to 50 selected by the g2~g 0 bits in the ocpc1 register . this is known as the programmable gain amplifer or pga. this pga can also be confgured to operate in the non-inverting, inverting or input of fset cancellation mode determined by the enocp1 and enocp0 bits in the ocpc0 register . after the current is converted and amplifed to a specifc voltage level, it will be compared with a reference voltage provided by an 8-bit d/a converte r. the 8-bit d/a converter power can be supplied by the external power pin, vdd or v ref, selected by the ocpvs bit in the ocpc0 register . the comparator output, cpout , will frst be fltered with a certain de-bounce time period selected by the fl t2~flt0 bits in the ocpc1 register. then a flt ered ocp digita l compara tor out put, ocpo, is obt ained to indicat e whether an over current condition occurs or not. the ocpo bit will be set to 1 if an over current condition occurs. o therwise, the o cpo bit is zero. o nce an over current event occurs , i.e., the converted voltage of t he ocp i nput c urrent i s gr eater t han t he re ference vo ltage, t he c orresponding i nterrupt will be generated if the relevant interrupt control bit is enabled. 8-?it d/a ocpda[7:0] filte? (to a/d inte?nal input) r1 r? (r1=?k) gain=1/5/10/15/?0/30/?0/50 ocpo s1 s0 s? s3 g[?:0] f flt =f h enocp[1:0] opamp vdd vref ocpvs ocpchy cpout flt[?:0] ocpao ocpint cmp (ocp flag) ocp0 ocp1 se?ies ?esisto?s ocps[1:0] s? over current protection block diagram
rev. 1.10 88 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 89 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu o ver current protection control registers overall operation of the over current protection is controlled using several registers. one register is used to provide the reference voltag es for the over current protection circuit. there are two registers used to cancel out the operational amplifer and comparator input offset. the remaining two registers are control registers which control the ocp function, d/a converter reference voltage select, pga gain select, comparator de-bounce time together with the hysteresis function. there are two control bits, ocps1 and ocps0, in the ctrl2 register used to confgure the ocp input coming from ocp0 or ocp1 pin or from the series resistors. as for the ocp0 or ocp1 pin control, there are revelant pin-shared c ontrol b its t o c onfgure t he oc p i nput p ins. for a m ore d etailed d escription r egarding the input of fset voltage cancellation procedures, refer to the corresponding input of fset cancellation sections. register name bit 7 6 5 4 3 2 1 0 ocpc0 enocp1 enocp0 ocpvs ocpchy ocpo ocpc1 g ? g1 g0 flt ? flt 1 flt 0 ocpda d7 d ? d5 d ? d3 d ? d1 d0 ocpocal oofm orsp oof5 o of ? oof3 o of ? oof1 oof0 ocpccal cpout cofm crsp cof ? cof3 cof ? cof1 cof0 ctrl ? sw_en led_s1 led_s0 led_ctl ocps1 ocps0 hv_ctl ocp register list ocpc0 register bit 7 6 5 4 3 2 1 0 na ? e enocp1 enocp0 ocpvs ocpchy ocpo r/w r/w r/w r/w r/w r por 0 0 0 0 0 bit 7~6 en ocp1~enocp0 : ocp function operating mode selection 00: ocp function disable d, s1 and s3 on, s0 and s2 off 01: ocp operates in non-inverter mode , s0 and s3 on, s1 and s2 off 10: ocp operates in inverter mode, s1 and s2 on, s0 and s3 off 11: ocp operates in calibration mode, s1 and s3 on, s0 and s2 off bit 5 ocpvs : ocp d/a converter reference voltage selection 0: from vdd pin 1: from vref pin bit 4 ocpchy : ocp comparator hysteresis function control 0: disable 1: enable bit 3~1 unimplemented, read as 0 bit 0 ocpo : ocp comparator filtered digital output fag 0: no over current condition occurs 1: over current condition occurs
rev. 1.10 88 de?e??e? 1?? ?01? rev. 1.10 89 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu ocpc1 register bit 7 6 5 4 3 2 1 0 na ? e g ? g1 g0 flt ? flt 1 flt 0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~3 g2~g0 : pga r2/r1 ratio selection 000: unity gain buffer (non-inverting mode) or gain= 1 (inverting mode) 001: r2/r1=5 010: r2/r1=10 011: r2/r1=15 100: r2/r1=20 101: r2/r1=30 110: r2/r1=40 111: r2/r1=50 these bits are used to select the r2/r1 ratio to obtain various gain values for inverting and non-inverting mode. the calculating formula of the pga gain for the inverting and non-inverting mode is described in the input v oltage range section. bit 2~0 flt 2~flt 0 : ocp output flter de-bounce time selection 000: no debounce 001: (1~2) t flt 010: (3~4) t flt 011: (7~8) t flt 100: (15~16) t flt 101: (31~32) t flt 110: (63~64) t flt 111: (127~128) t flt note: f flt =f h, t flt =1/f flt ocpda register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 ocp d /a converter data register bit 7 ~ bit 0 ocp d /a converter output = (dac reference voltage/256) d [7:0] ocpocal register bit 7 6 5 4 3 2 1 0 na ? e oofm orsp oof5 oof ? oof3 oof ? oof1 oof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 oofm : ocp operational amplifer input offset cancellation mode enable control 0: input offset cancellation mode disabled 1: input offset cancellation mode enabled this bi t i s use d t o c ontrol t he ocp op erational a mplifier i nput of fset c ancellation function. the enocp1 and enocp0 bits must frst be set to 11 and then the oofm bit must be set to 1 followed by the cofm bit being setting to 0, then the operational amplifier input of fset cancel lation mode wil l be enabled. refe r to the opera tional amplifier input of fset cancellation section for the detailed of fset cancellation procedures.
rev. 1.10 90 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 91 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu bit 6 orsp : ocp operational amplifer input offset cancellation reference input select 0: operational amplifer negative input is selected 1: operational amplifer positive input is selected bit 5~0 oof5~oof0 : ocp operational amplifer input offset cancellation value this 6-bit feld is used to perform the operational amplifer input of fset cancellation operation and the value for the ocp operational amplifer input of fset cancellation can be restored i nto this bit feld. more detailed information is described in the operational amplifer input offset cancellation section. ocpccal register bit 7 6 5 4 3 2 1 0 na ? e cpout cofm crsp cof ? cf3 cof ? cof1 cof0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 cpout : ocp comparator or operation amplifer digital output in input offset cancellation mode 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage this bit is used to indicate whether the positive input voltage is greater than the negative input voltage when the ocp operates in the input of fset cancellation mode. if the cpout is set to 1, the positive input voltage is greater than the negative input voltage. otherwise, the positive input voltage is less than the negative input voltage. bit 6 cofm : ocp comparator input offset cancellation mode enable control 0: input offset cancellation mode disabled 1: input offset cancellation mode enabled this bit is used to control the ocp comparator input of fset cancellatio n function. the enocp1 and enocp0 bits must first be set to 1 1 and then the cofm bit must be set to 1 followed by the oofm bit being setting to 0, then the comparator input offset cancellation mode will be enabled. refer to the comparator input of fset cancellation section for the detailed offset cancellation procedures. bit 5 crsp : ocp comparator input offset cancellation reference input select 0: comparator negative input is selected 1: comparator positive input is selected bit 4~0 cof4~cof0 : ocp comparator input offset cancellation value this 5-bit feld is used to perform the comparator input of fset cancellation operation and the value for the ocp comparator input of fset cancellation can be restored into this bit feld. more detailed informa tion is described in the comparat or input of fset cancellation section.
rev. 1.10 90 de?e??e? 1?? ?01? rev. 1.10 91 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu ctrl2 register bit 7 6 5 4 3 2 1 0 na ? e sw_en led_s1 led_s0 led_ctl ocps1 ocps0 hv_ctl r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 1 bit 7 se_en : sw control described elsewhere. bit 6 unimplemented, read as 0 bit 5~4 led_s1 ~led_s0 : control signal type selection for led_en described elsewhere. bit 3 led_ctl : led control described elsewhere. bit 2~1 ocps1 ~ocps0 : ocp input selection 00: from ocp0 pin 01: from ocp1 pin 1x: from s eries resistors bit 0 hv_ctl : high v oltage control described elsewhere. i nput voltage range together with dif ferent pga operat ing modes, the input voltage on the ocp pin can be positive or negative to provide diverse applications for the device. the pga output for the positive or negative input voltage is respectively calculated based on different formulas and described by the following. ? for input voltage v in > 0, the pga operates in the non-inverting mode and the pga output is obtained using the formula below: in 1 2 out vx ) r r (1v += ? when the pga operates in the non-inverting mode by setting the enocp1 and enocp0 bits to 01 with unity gain select by setting the g2~g0 to 000, the pga will act as an unit-gain buffer whose output is equal to v in . in out vv = ? for input voltage 0 >v in >-0. , the pga operates in the inverting mode and the pga output is obtained using the formula below. note that if the input voltage is negative, it can not be lower than -0. v which will result in current leakage. in 1 2 out vx r r v ?=
rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 93 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu offset calibration to operate in the input of fset cance llation mode for the ocp circuit, the enocpc1 and enocpc0 bits s hould frst be set to 1 1. for operational amplif er and comparator input of fset cancellation, the procedures are similar except for setting the respective control bits. operational amplifer input offset cancellation ? step 1: set enocp [1:0] = 11, oofm=1 and cofm=0, the ocp will operate in the operational amplifer input offset cancellation mode. ? step 2: set oof [5:0] = 000000 and read the cpout bit. ? step 3: increase the oof [5:0] value by 1 and then read the cpout bit. ? if the cpout bit state has not changed, then repeat step 3 until the cpout bit state has changed. ? if the cpout bit state has changed, record the oof value as v o os1 and then go to step 4. ? step 4: set oof [5:0] = 111111 and read the cpout bit. ? step 5: decrease the oof [5:0] value by 1 and then read the cpout bit. ? if the cpout bit state has not changed, then repeat step 5 until the cpout bit state has changed. ? if the cpout bit state has changed, record the oof value as v o os2 and then go to step 6. ? step 6: restore the operational amplifer input offset cancellation value v o os into the oof [5:0] bit feld. the offset cancellation procedure is now fnished. where 2 voos2 voos1 osv + = o comparator input offset cancellation ? step 1: set enocp [1:0] = 11, cofm=1 and oofm=0, the ocp will now operate in the comparator input offset cancellation mode. s4 is on (s4 is used for calibration mode, in normal mode operation, it is off). ? step 2: set cof [4:0] = 00000 and read the cpout bit. ? step 3: increase the cof [4:0] value by 1 and then read the cpout bit. ? if the cpout bit state has not changed, then repeat step 3 until the cpout bit state has changed. ? if the cpout bit state has changed, record the cof value as vcos1 and then go to step 4. ? step 4: set cof [4:0] = 11111 and read the cpout bit. ? step 5: decrease the cof [4:0] value by 1 and then read the cpout bit. ? if the cpout bit state has not changed, then repeat step 5 until the cpout bit state has changed. ? if the cpout bit state has changed, record the cof value as vcos2 and then go to step 6. ? step 6: restore the comparator input offset cancellation value vcos into the cof [4:0] bit feld. the offset cancellation procedure is now fnished. where 2 vcos2 vcos1 vcos + =
rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 93 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu emergency light application description in the emer gency light products , a m cu determines to buck char ge or boos t char ge to provide the required emer gency lighting power according to the conditions of the mains supply and the chargeable battery . this device has includes a range of functions relate d to emer gency lights. using an internal power mos, the device can easily implement the above functions while meeting the associated chinese national standards. the related operations are described as below. charge under normal mains supply an emer gency light is usually powered by the mains supply with ac power being converted to dc power. w hen t he v oltage i s wi thin 1 2v, i t c an b e d irectly c onnected t o t he hv_ in p in t o p rovide power for the mcu and other circu its. in this case, for a 1.2v char geable battery , buck char ge can be implemented by turning on the m0 and m4 (controlled by pwm outputs) as well as the ba t_in pin externally connected with an inductor , a schottky diode and the battery . the a/d converter can be used for char ging current control. for a better buck char ge result, connect an external nmos to the pa7 pin for synchronous rectifcation. analog battery boost charge under normal mains supply turn of f t he m0, use t he m4 a nd p a7 pi n for c omplementary pw m c ontrol, a nd t hen e xternally connect an nmos and an inductor to boost the battery voltage or current to a high level required by the led lighting. after the high voltage has been generated, it can be read by the internal resistor divider which is enabled using the sw_en bit to implement constant voltage feedback control. for a better boost char ge result, connect a schottky diode in parallel between the ba t_in pin and the hv_out pin. refer to the application circuit section for more details. buzzer driving the m1 a nd m2 t ogether form t he buz zer de dicated out put pi n, i t i s c ontrolled by t he bz _s0 a nd bz_s1 bits to output a pwm signal or a constant high/low level. led driving the led_out pin is a led driving output pin. the internal high voltage power is transmitted to this pin by the m3 mos to driving the led. whether to use a pwm signal for led dimming and constant current control or to enable/disable the ldo_out pin output is determined by the led_ s0 and led_s1 bits.
rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 95 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu high voltage mos this device integrates several high voltage mos transistors with level shift functions, which along with the ldo regulator are used for power control, led control, buzzer driver control and char ge/ discharge control. ldo (5v/ 50 ?a ) hv _ in (7v~ 1? v) charge / discharge control buzzer driver circuit level shift co?ple?enta?y pwm level shift level shift level shift led control circuit hv _ out v in led _ out bz bat _ in vdd m0 m1 m? m3 m? led _ en hv _ en hv pa7/ pwm 0l 5v ?00 k 100 k sw 0 sw 1 to adc o? ocp input sw _ en pwm 0h
rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 95 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu the driving signals for each mos control are furtherly described in the following control circuits. hv _s0 hv _ ctl m0 ( powe? sw ) level-shift mux pwm signal ( tm ?) pwm signal ( tm 1) pwm signal ( tm 0) hv _s1 00 01 10 11 bz _s0 mux pwm signal ( tm ?) bz _ ctl m1 m? ( buzze? d?ive? ) level-shift bz _s1 pwm signal ( tm 1) pwm signal ( tm 0) 00 01 10 11 led _s0 m3 led _ ctl ( led sw ) level-shift mux pwm signal ( tm ?) pwm signal ( tm 1) pwm signal ( tm 0) led _s1 00 01 10 11
rev. 1.10 9 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 97 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu level-shift m? mux 1 0 1 pwml pwmh 1 0 dcpd _ ctl 0 0 pwm 0l pwm 0h dcpd _ ctl 1 mux control registers these two regiters are control regiters which select the driving signal for level shift function in each control circuit shown in the above block diagram. ctrl2 register bit 7 6 5 4 3 2 1 0 na ? e sw_en led_s1 led_s0 led_ctl ocps1 ocps0 hv_ctl r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 1 bit 7 se_en : sw control 0: disable 1: enable bit 6 unimplemented, read as 0 bit 5~4 led_s1 ~led_s0 : control signal type selection for led enable 00: normal signal (high/low) 01: pwm signal from tm0 10 : pwm signal from tm1 11: pwm signal from tm2 when these bits are set to 00, the control signal is determined by the led_ctl bit. bit 3 led_ctl : led control 0: off 1: on bit 2~1 ocps1 ~ocps0 : ocp input selection described elsewhere. bit 0 hv_ctl : high v oltage control 0: off 1: on
rev. 1.10 9? de?e??e? 1?? ?01? rev. 1.10 97 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu ctrl5 register bit 7 6 5 4 3 2 1 0 na ? e hv_s1 hv_s0 dcpd_ctl1 dcpd_ctl0 bz_s1 bz_s0 bz_ctl r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~5 hv_s1 ~hv_s0 : control signal type selection for hv enable 00: normal signal (high/low) 01: pwm signal from tm0 10 : pwm signal from tm1 11: pwm signal from tm2 when these bits are set to 00, the control signal is determined by the hv_ctl bit. bit 4 dcpd_ctl1 : dc to dc pwup control 0: pwm0h always high 1: pwm0h signal from pwmh when this bit is cleared to zero, pwm0h is always high level, m4 is turned of f. when this bit is set high, m4 is controlled by pwm0h whose signal is from pwmh, it means that m4 is only controlled by tm0, it can not use tm1 and tm2. refer to the complementary pwm output section for more details. bit 3 dcpd_ctl0 : dc to dc pwdn control 0: pwm0l always low 1: pwm0l signal from pwml bit 2~1 bz_s1 ~bz_s0 : control signal type selection for buzzer enable 00: normal signal (high/low) 01: pwm signal from tm0 10 : pwm signal from tm1 11: pwm signal from tm2 when these bits are set to 00, the control signal is determined by the bz_ctl bit. bit 0 bz_ctl : buzzer control 0: off 1: on
rev. 1.10 98 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 99 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt a nd i nternal i nterrupts f unctions. t he e xternal i nterrupt i s g enerated b y t he a ction o f the external int 0 and int1 pins, while the internal interrupts are generated by various internal functions such as the tms, o ver c urrent p rotection function, t ime base, l vd, eeprom and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the interrupt registers fall into three categories. the frst is the intc0~intc 2 registers which setup the primary interrupts, the second is the mfi0~mfi 3 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes glo ? al emi intn pin intne intnf n=0 o ? 1 ocp ocpe ocpf a/d conve ? te ? ade adf multi-fun ? tion mfne mfnf n=0~3 ti ? e base tbne tbnf n=0 o ? 1 lvd lve lvf eeprom dee def tm tnpe tnpf n=0 ~ ? tnae tnaf interrupt register bit naming conventions interrupt register contents name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ int1s1 int1s0 int0s1 int0s0 intc0 int0f ocpf int0e ocpe emi intc1 mf3f mf ? f mf1f mf0f mf3e mf ? e mf1e mf0e intc ? int1f tb1f tb0f adf int1e tb1e tb0e ade mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi ? t ? af t ? pf t ? ae t ? pe mfi3 def lv f dee lv e
rev. 1.10 98 de?e??e? 1?? ?01? rev. 1.10 99 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu integ register bit 7 6 5 4 3 2 1 0 na ? e int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 4 unimplemented, read as 0 b it 3 ~ 2 int1s1, int1s0 : defnes int1 interrupt active edge 00 : disabled interrupt 0 1: rising edge interrupt 10 : falling edge interrupt 11 : dual edge interrupt b it 1 ~ 0 int0s1, int0s0 : defnes int0 interrupt active edge 00 : disabled interrupt 0 1: rising edge interrupt 10 : falling edge interrupt 11 : dual edge interrupt intc0 register bit 7 6 5 4 3 2 1 0 na ? e int0f ocpf int0e ocpe emi r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7 unimplemented, read as 0 b it 6 int0f : external interrupt 0 request fag 0: no request 1: interrupt request b it 5 o cpf : over current protection interrupt request fag 0: no request 1: interrupt request b it 4 unimplemented, read as 0 b it 3 int0e : external interrupt 0 control 0: disable 1: enable b it 2 ocpe : over current protection interrupt control 0: disable 1: enable b it 1 unimplemented, read as 0 b it 0 emi : global interrupt control 0: disable 1: enable
rev. 1.10 100 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 101 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu intc 1 register bit 7 6 5 4 3 2 1 0 na ? e mf3f mf ? f mf1f mf0f mf3e mf ? e mf1e mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 mf3f : multi-function interrupt 3 request fag 0: no request 1: interrupt request b it 6 mf2f : multi-function interrupt 2 request fag 0: no request 1: interrupt request b it 5 mf1f : multi-function interrupt 1 request fag 0: no request 1: interrupt request b it 4 mf0f : multi-function interrupt 0 request fag 0: no request 1: interrupt request b it 3 mf3e : multi-function interrupt 3 control 0: disable 1: enable b it 2 mf2e : multi-function interrupt 2 control 0: disable 1: enable b it 1 mf1e : multi-function interrupt 1 control 0: disable 1: enable b it 0 mf0e : multi-function interrupt 0 control 0: disable 1: enable intc2 register bit 7 6 5 4 3 2 1 0 na ? e int1f tb1f tb0f adf int1e tb1e tb0e ade r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 int 1f : external interrupt 1 request fag 0: no request 1: interrupt request b it 6 tb1f : t ime base 1 interrupt request fag 0: no request 1: interrupt request b it 5 tb0f : t ime base 0 interrupt request fag 0: no request 1: interrupt request b it 4 adf : a/d converter interrupt request fag 0: no request 1: interrupt request b it 3 int 1e : external interrupt 1 control 0: disable 1: enable
rev. 1.10 100 de?e??e? 1?? ?01? rev. 1.10 101 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu b it 2 tb 1e : t ime base 1 interrupt control 0: disable 1: enable b it 1 tb 0e: time base 0 interrupt control 0: disable 1: enable b it 0 ad e : a/d converter interrupt control 0: disable 1: enable mfi0 register bit 7 6 5 4 3 2 1 0 na ? e t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~6 unimplemented, read as 0 b it 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request b it 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request b it 3~2 unimplemented, read as 0 b it 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable b it 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 na ? e t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 6 unimplemented, read as 0 b it 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request b it 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request b it 3 ~ 2 unimplemented, read as 0 b it 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable b it 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 103 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu mfi 2 register bit 7 6 5 4 3 2 1 0 na ? e t ? af t ? pf t ? ae t ? pe r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 6 unimplemented, read as 0 b it 5 t 2af : tm 2 comparator a match interrupt request fag 0: no request 1: interrupt request b it 4 t 2pf : tm 2 comparator p match interrupt request fag 0: no request 1: interrupt request b it 3 ~ 2 unimplemented, read as 0 b it 1 t2ae : tm 2 comparator a match interrupt control 0: disable 1: enable b it 0 t2pe : tm 2 comparator p match interrupt control 0: disable 1: enable mfi3 register bit 7 6 5 4 3 2 1 0 na ? e def lv f dee lv e r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 6 unimplemented, read as 0 b it 5 def : data eeprom interrupt request fag 0: no request 1: interrupt request b it 4 lv f : lvd interrupt request fag 0: no request 1: interrupt request b it 3 ~ 2 unimplemented, read as 0 b it 1 de e : data eeprom interrupt control 0: disable 1: enable b it 0 lv e : lvd interrupt control 0: disable 1: enable
rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 103 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/ d conversion completion etc, the relevant interrupt request fag wi ll be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. all o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 105 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu int0 pin int1 pin int0f int1f int0e int1e emi 0?h emi 08h emi 0ch ti?e base 0 tb0f tb0e emi 1ch inte??upt na?e request flags ena?le bits maste? ena?le vector emi auto disa?led in isr p?io?ity high low tm0p t0pf t0pe tm0a t0af t0ae m. fun?t. 0 mf0f mf0e inte??upts ?ontained within multi-fun?tion inte??upts xxe ena?le bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr emi ?0h emi ??h m. fun?t. 1 mf1f mf1e ti?e base 1 tb1f tb1e a/d adf ade emi 18h emi 10h lvd lvf lve m. fun?t. 3 mf3f mf3e eeprom def dee tm1p t1pf t1pe tm1a t1af t1ae ocp ocpf ocpe emi ?8h 1?h emi m. fun?t. ? mf?f mf?e tm?p t?pf t?pe tm?a t?af t?ae interrupt structure external interrupt the external interrupts are controlled by signal transitions on the pins int0 ~ int1 . an external interrupt request will take place when the external interrupt request fags, int0f ~ int1 f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e ~int1 e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register as well as the relevant pin-shared functio n selection bits . when the interrupt is enabled, the stack is not full and the correct transition type appears on the extern al interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f ~int 1 f, will be automatically reset and the emi bit will be automatically cleare d to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function.
rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 105 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu ocp interrupt an ocp i nterrupt re quest wi ll t ake pl ace whe n t he ove r c urrent pro tection in terrupt re quest fa g, ocpf, is set, which occurs when the over current protection function detects an over current condition. t o allow the program to branch to its res pective interrupt vector addres s, the global interrupt enable bit, emi, and over current protection interrupt enabl e bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the ocp interrupt vector , will take place. when the over current protection interrupt is serviced, the emi bit wi ll be a utomatically cl eared t o disabl e othe r i nterrupts a nd the i nterrupt reque st fa g will be also automatically cleared. multi-function interrupt within the device there are four multi-function interrupts. unlike the other independent interrupts, these int errupts have no i ndependent sourc e, but rat her are form ed from other exi sting i nterrupt sources, na mely t he t m int errupts , l vd int errupt a nd e eprom int errupt. a mult i-function interrupt request will take place when any of the multi-function interrupt request fags, mfnf are set. t he mul ti-function i nterrupt fl ags wi ll be se t whe n a ny of t heir i ncluded func tions ge nerate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained wi thin e ach of mul ti-function i nterrupt oc curs, a subrout ine c all t o one of t he mul ti- function interrupt vectors will take place. when the interrupt is service d, the related multi-function request fa g, wi ll be aut omatically reset a nd t he emi bi t wi ll be aut omatically cl eared t o di sable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request flags from the original source of the multi- function i nterrupts, na mely t he t m int errupts , l vd int errupt a nd e eprom int errupt wi ll not be automatically reset and must be manually reset by the application program. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/ d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector a ddress, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.10 10 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 107 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. tbc register bit 7 6 5 4 3 2 1 0 na ? e tbon tbck tb11 tb10 tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 b it 7 tbon : tb0 and tb1 control bit 0: disable 1: enable b it 6 tbck : select f tb clock 0: f tbc 1: f sys /4 b it 5 ~ 4 tb1 1 ~ tb10 : select t ime base 1 t ime-out period 00: 2 12 /f tb 01: 2 13 /f tb 10: 2 14 /f tb 11: 2 15 /f tb b it 3 unimplemented, read as 0 b it 2 ~ 0 tb02 ~ tb00 : select t ime base 0 t ime-out period 000: 2 8 /f tb 001: 2 9 /f tb 010: 2 10 /f tb 011: 2 11 /f tb 100: 2 12 /f tb 101: 2 13 /f tb 110: 2 14 /f tb 111: 2 15 /f tb                         
        
          
      time base interrupt
rev. 1.10 10? de?e??e? 1?? ?01? rev. 1.10 107 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu eeprom interrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def , is set, which occurs when an eeprom w rite cycl e ends. t o allow the program to branch to its respective interrupt vector a ddress, t he gl obal i nterrupt e nable bi t, e mi, a nd e eprom int errupt e nable bi t, de e, and ass ociated multi-function interrupt enable bit , mf3e, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vector , will take place. when the eeprom interrupt is serviced, the emi bit will be automatica lly cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the lvd interrupt is contained within the multi-function interrupt. an l vd interrupt request will take p lace wh en t he l vd i nterrupt r equest fa g, l vf, i s se t, wh ich o ccurs wh en t he l ow v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrup t vector address, the global interrupt enable bit, emi, and low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit , mf3e, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the l vd interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit will be automatica lly cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the l vd interrupt request fag , lvf , will not be automatically cleared, it has to be cleared by the application program. tm interrupt s the periodic t ype tm s each has two interrupts. all of the tm interrupts are contained within the multi-function interrupts. for the periodic t ype tms there are two inte rrupt request fags t n pf and tn af and two enable bits t n pe and t nae. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or comparator a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the respective tm interrupt enable bit, and associated multi-function interrupt enable bit , mfnf , must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant tm interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program.
rev. 1.10 108 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 109 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltag e may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the m ulti-function interrupt reques t f ags, m f0f~mf 3 f, w ill be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.10 108 de?e??e? 1?? ?01? rev. 1.10 109 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu low voltage detector C lvd the device has a low v oltage detector function, also known as l vd. this enable s the device to monitor the power supply voltage, v dd , and provide s a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a low volta ge condition will be detemined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enabl e the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 na ? e lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 b it 7 ~ 6 unimplemented, read as 0 b it 5 lvdo : lvd output flag 0: no low v oltage detect 1: low v oltage detect b it 4 lvden : low v oltage detector control 0: disable 1: enable b it 3 unimplemented, read as 0 b it 2~0 vl vd2 ~ vlvd0 : select lvd v oltage 000: 2.0v 00 1: 2.2v 010 : 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.10 110 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 111 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu lvd operation the low v oltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2. 0 v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. after enabling the low v oltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the l vdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions.              lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts , providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition . in this case, the l vf interrupt request fag will be set, causing an interru pt to be generated if v dd falls below the preset l vd voltage . this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the l vf fag should be frst set high before the devic e enters the sleep or idle mode. confguration option confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programmi ng tools, once they are sel ected t hey cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator option 1 hirc f ? equen ? y sele ? tion: 1. ? 0 mhz ? . 1 ? mhz 3. 1 ? mhz
rev. 1.10 110 de?e??e? 1?? ?01? rev. 1.10 111 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu application circuit emergency light application circuit (led under 0.6w) ac input 220v v in hv_in vss led <0.6w 330 ? hv_out v in hv_out led_out bz bat_in pa0 pa2 HT45FH4J 16nsop ocp0/pa6 an0/pa1 an1/pa3 pa4 an3/ocp1/pa5 0.1f 47f/16v 0.5? 1.2v 47h 10 ? pwm0/pa7 hvss 220f 1.5k ? 20k ? rcc circuits (output dc 7v) hv_out 1.2v battery 0.1f 100f vdd 4.7f 5v v_bat hv_out 7~12v 140ma reduce standby current circuits 100ma 0.1f 0.1f 20k ? 18k ? 100k ? 100 ? 1m ? v in
rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 113 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu emergency light application circuit (led over 1w) ac input 220v v in hv_in vss 330 ? hv_out v in hv_out bz bat_in pa0 pa2 HT45FH4J 16nsop an0/pa1 an1/pa3 pa4 an3/ocp1/pa5 0.1f 100f/16v 1.2v 47h 10 ? pwm0/pa7 hvss 220f 1.5k ? 20k ? rcc circuits (output dc 7v) hv_out 1.2v battery 0.1f 100f vdd 4.7f 5v v_bat hv_out 7~12v 140ma reduce standby current circuits 0.1f 20k ? 18k ? 100k ? 1m ? v in led >0.6w led_out ocp0/pa6 0.5 ? hv_out 20k ? 0.1f 100 ?
rev. 1.10 11 ? de?e??e? 1?? ?01? rev. 1.10 113 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 115 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.10 11 ? de?e??e? 1?? ?01? rev. 1.10 115 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [ ? ] add data me ? o ? y to acc 1 z ? c ? ac ? ov addm a ? [ ? ] add acc to data me ? o ? y 1 note z ? c ? ac ? ov add a ? x add i ?? ediate data to acc 1 z ? c ? ac ? ov adc a ? [ ? ] add data me ? o ? y to acc with ca ?? y 1 z ? c ? ac ? ov adcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y 1 note z ? c ? ac ? ov sub a ? x su ? t ? a ? t i ?? ediate data f ? o ? the acc 1 z ? c ? ac ? ov sub a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc 1 z ? c ? ac ? ov subm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y 1 note z ? c ? ac ? ov sbc a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov sbcm a ? [ ? ] su ? t ? a ? t data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y 1 note z ? c ? ac ? ov daa [ ? ] de ? i ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 note c logic operation and a ? [ ? ] logi ? al and data me ? o ? y to acc 1 z or a ? [ ? ] logi ? al or data me ? o ? y to acc 1 z xor a ? [ ? ] logi ? al xor data me ? o ? y to acc 1 z andm a ? [ ? ] logi ? al and acc to data me ? o ? y 1 note z orm a ? [ ? ] logi ? al or acc to data me ? o ? y 1 note z xorm a ? [ ? ] logi ? al xor acc to data me ? o ? y 1 note z and a ? x logi ? al and i ?? ediate data to acc 1 z or a ? x logi ? al or i ?? ediate data to acc 1 z xor a ? x logi ? al xor i ?? ediate data to acc 1 z cpl [ ? ] co ? ple ? ent data me ? o ? y 1 note z cpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc 1 z increment & decrement inca [ ? ] in ?? e ? ent data me ? o ? y with ? esult in acc 1 z inc [ ? ] in ?? e ? ent data me ? o ? y 1 note z deca [ ? ] de ?? e ? ent data me ? o ? y with ? esult in acc 1 z dec [ ? ] de ?? e ? ent data me ? o ? y 1 note z rotate rra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc 1 none rr [ ? ] rotate data me ? o ? y ? ight 1 note none rrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y 1 note c rla [ ? ] rotate data me ? o ? y left with ? esult in acc 1 none rl [ ? ] rotate data me ? o ? y left 1 note none rlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y 1 note c
rev. 1.10 11 ? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 117 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu mnemonic description cycles flag affected data move mov a ? [ ? ] move data me ? o ? y to acc 1 none mov [ ? ] ? a move acc to data me ? o ? y 1 note none mov a ? x move i ?? ediate data to acc 1 none bit operation clr [ ? ].i clea ? ? it of data me ? o ? y 1 note none set [ ? ].i set ? it of data me ? o ? y 1 note none branch jmp add ? ju ? p un ? onditionally ? none sz [ ? ] skip if data me ? o ? y is ze ? o 1 note none sza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc 1 note none sz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o 1 note none snz [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o 1 note none siz [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o 1 note none sdz [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o 1 note none siza [ ? ] skip if in ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none sdza [ ? ] skip if de ?? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 note none call add ? su ?? outine ? all ? none ret retu ? n f ? o ? su ?? outine ? none ret a ? x retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc ? none reti retu ? n f ? o ? inte ?? upt ? none table read tabrd [ ? ] read table (specifc page) to tblh and data memory ? note none tabrdc [ ? ] read ta ? le ( ? u ?? ent page) to tblh and data me ? o ? y ? note none tabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y ? note none miscellaneous nop no ope ? ation 1 none clr [ ? ] clea ? data me ? o ? y 1 note none set [ ? ] set data me ? o ? y 1 note none clr wdt clea ? wat ? hdog ti ? e ? 1 to ? pdf clr wdt1 p ? e- ? lea ? wat ? hdog ti ? e ? 1 to ? pdf clr wdt ? p ? e- ? lea ? wat ? hdog ti ? e ? 1 to ? pdf swap [ ? ] swap ni ?? les of data me ? o ? y 1 note none swapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc 1 none halt ente ? powe ? down ? ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the t o and pdf flags may be af fected by the execution status. the t o and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.10 11 ? de?e??e? 1?? ?01? rev. 1.10 117 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.10 118 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 119 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.10 118 de?e??e? 1?? ?01? rev. 1.10 119 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.10 1 ? 0 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?1 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.10 1?0 de?e??e? 1?? ?01? rev. 1.10 1 ? 1 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?3 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 3 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?5 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 5 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.10 1 ?? de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?7 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product t ape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.10 1?? de?e??e? 1?? ?01? rev. 1.10 1 ? 7 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu 16-pin nsop (150mil) outline dimensions               symbol dimensions in inch min. nom. max. a 0. ? 3 ? bsc b 0.15 ? bsc c 0.01 ? 0.0 ? 0 c 0.390 bsc d 0.0 ? 9 e 0.050 bsc f 0.00 ? 0.010 g 0.01 ? 0.050 h 0.00 ? 0.010 0 8 symbol dimensions in mm min. nom. max. a ? bsc b 3.9 bsc c 0.31 0.51 c 9.9 bsc d 1.75 e 1. ? 7 bsc f 0.10 0. ? 5 g 0. ? 0 1. ? 7 h 0.10 0. ? 5 0 8
rev. 1.10 1 ? 8 de ? e ?? e ? 1 ?? ? 01 ? rev. 1.10 1?9 de?e??e? 1?? ?01? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu 20 -pin ssop (150mil) outline dimensions              symbol dimensions in inch min. nom. max. a 0. ? 3 ? bsc b 0.155 bsc c 0.008 0.01 ? c 0.3 ? 1 bsc d 0.0 ? 9 e 0.0 ? 5 bsc f 0.00 ? 0.0098 g 0.01 ? 0.05 h 0.00 ? 0.01 0 D 8 symbol dimensions in mm min. nom. max. a ? bsc b 3.9 bsc c 0. ? 0 0.30 c 8. ?? bsc d 1.75 e 0. ? 35 bsc f 0.10 0. ? 5 g 0. ? 1 1. ? 7 h 0.10 0. ? 5 0 D 8
rev. 1.10 1?8 de?e??e? 1?? ?01? rev. 1.10 1 ? 9 de ? e ?? e ? 1 ?? ? 01 ? HT45FH4J emergency light flash mcu HT45FH4J emergency light flash mcu copy ? ight ? ? 01 ? ? y holtek semiconductor inc. the info ?? ation appea ? ing in this data sheet is ? elieved to ? e a ?? u ? ate at the ti ? e of pu ? li ? ation. howeve ?? holtek assu ? es no ? esponsi ? ility a ? ising f ? o ? the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek ? akes no wa ?? anty o ? ? ep ? esentation that su ? h appli ? ations will ? e suita ? le without fu ? the ? ? odifi ? ation ? no ? ? e ? o ?? ends the use of its p ? odu ? ts fo ? appli ? ation that ? ay p ? esent a ? isk to hu ? an life due to ? alfun ? tion o ? othe ? wise. holtek's p ? odu ? ts a ? e not autho ? ized fo ? use as ?? iti ? al ? o ? ponents in life suppo ? t devi ? es o ? syste ? s. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek. ? o ? .tw.


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